MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 113

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

8.3.1 Bus Timing
8.3.2 Clock Start-Up from POR or LVI Reset
8.3.3 Clocks in Stop and Wait Modes
8.4 Reset and System Initialization
MC68HC908AB32
MOTOROLA
—
Rev. 1.0
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has been completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.
Upon exit from stop mode (by an interrupt, break, or reset), the SIM
allows CGMXCLK to clock the SIM counter. The CPU and peripheral
clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 CGMXCLK cycles. (See
Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
The MCU has the following reset sources:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
System Integration Module (SIM)
Go to: www.freescale.com
Section 9. Clock Generator Module
System Integration Module (SIM)
Reset and System Initialization
(CGM).
Technical Data
8.7.2 Stop
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