MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 25
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MC68HC908AB32
Manufacturer Part Number
MC68HC908AB32
Description
HCMOS Microcontroller Unit
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AB32.pdf
(392 pages)
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MC68HC908AB32
MOTOROLA
—
Rev. 1.0
Figure
16-1 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
16-2 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 282
16-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 283
16-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 287
16-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
16-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 288
16-7 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 290
16-8 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . . 291
16-9 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 293
16-10 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 294
16-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 297
16-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
16-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 304
16-14 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . . 306
16-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
17-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 312
17-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 316
17-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 316
17-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
17-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . 318
17-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 319
17-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
17-8 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 320
17-9 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 321
17-10 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
17-11 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . 323
17-12 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 324
17-13 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
17-14 Port D Input Pullup Enable Register (PTDPUE) . . . . . . . . . . . 325
17-15 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 326
17-16 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 328
17-17 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
17-18 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . . 329
17-19 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . . 330
17-20 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Freescale Semiconductor, Inc.
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