MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 360
MC68HC908AB32
Manufacturer Part Number
MC68HC908AB32
Description
HCMOS Microcontroller Unit
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AB32.pdf
(392 pages)
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Low-Voltage Inhibit (LVI)
21.4 Functional Description
Technical Data
360
NOTE:
Figure 21-1
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWRD, enables the LVI to monitor
V
generate a reset when V
at or below that level for 9 or more consecutive CPU cycles. Setting the
LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop
mode.
LVISTOP, LVIPWRD, and LVIRSTD are in the configuration register 1
(CONFIG1).
details of the LVI’s configuration bits. Once an LVI reset occurs, the
MCU remains in reset until V
causes the MCU to exit reset.
Reset
output of the comparator controls the state of the LVIOUT flag in the LVI
status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
Where LVI trip falling voltage LVI
and LVI trip rising voltage LVI
(See
DD
Freescale Semiconductor, Inc.
voltage. The LVI reset bit, LVIRSTD, enables the LVI module to
For More Information On This Product,
Section 23. Electrical
DETECTOR
for details of the interaction between the SIM and the LVI. The
LOW V
V
DD
DD
Go to: www.freescale.com
shows the structure of the LVI module. The LVI is enabled
See Section 6. Configuration Register (CONFIG)
Low-Voltage Inhibit (LVI)
Figure 21-1. LVI Module Block Diagram
V
V
FROM CONFIG1
DD
DD
LVIPWRD
> LVI
LVI
Trip
Trip
DD
= 1
= 0
falls below a voltage, LVI
Specifications.)
DD
TRIPR
See 8.4.2.5 Low-Voltage Inhibit (LVI)
TO LVISR
rises above a voltage, LVI
LVIOUT
TRIPF
= V
STOP INSTRUCTION
FROM CONFIG1
= V
LVII
LVIRSTD
LVII
+ H
LVI
MC68HC908AB32
TRIPF
FROM CONFIG1
, and remains
LVISTOP
LVI RESET
TRIPR
MOTOROLA
—
, which
Rev. 1.0
for
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