MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 361

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

21.4.1 Polled LVI Operation
21.4.2 Forced Reset Operation
21.4.3 False Reset Protection
MC68HC908AB32
MOTOROLA
—
Rev. 1.0
Address:
Reset:
In applications that can operate at V
software can monitor V
register 1, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
In applications that require V
enabling LVI resets allows the LVI module to reset the MCU when V
falls below the LVI
more consecutive CPU cycles. In configuration register 1, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
The V
supply noise. In order for the LVI module to reset the MCU, V
remain at or below the LVI
cycles. V
MCU out of reset.
Read: LVIOUT
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
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$FE0F
Bit 7
0
DD
pin level is digitally filtered to reduce false resets due to power
must be above LVI
Go to: www.freescale.com
Figure 21-2. LVI I/O Register Summary
Low-Voltage Inhibit (LVI)
= Unimplemented
6
0
0
TRIPF
DD
level and remains at or below that level for 9 or
5
0
0
by polling the LVIOUT bit. In configuration
TRIPF
DD
TRIPR
to remain above the LVI
level for 9 or more consecutive CPU
4
0
0
DD
for only one CPU cycle to bring the
levels below the LVI
3
0
0
2
0
0
Low-Voltage Inhibit (LVI)
Functional Description
TRIPF
1
0
0
Technical Data
TRIPF
DD
level,
must
level,
Bit 0
0
0
361
DD