MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 291

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

16.7 Queuing Transmission Data
MC68HC908AB32
MOTOROLA
—
Rev. 1.0
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the transmit
data register only when the SPTE bit is high.
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA: CPOL = 1:0).
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
CPHA:CPOL = 1:0
WRITE TO SPDR
1
2
3
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
5
6 CPU READS SPSCR WITH SPRF BIT SET.
Freescale Semiconductor, Inc.
READ SPSCR
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
READ SPDR
For More Information On This Product,
Serial Peripheral Interface Module (SPI)
SPSCK
SPTE
SPRF
MOSI
Figure 16-8. SPRF/SPTE CPU Interrupt Timing
Go to: www.freescale.com
1
MSB BIT
BYTE 1
2
6
BIT
5
3
BIT
4
BIT
3
BIT
2
BIT
Serial Peripheral Interface Module (SPI)
1
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
10
7 CPU READS SPDR, CLEARING SPRF BIT.
8
9
LSB MSB BIT
5
4
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
BYTE 2
6
Figure 16-8
6
7
BIT
Queuing Transmission Data
5
8
BIT
4
BIT
3
BIT
2
BIT
1
shows the
Technical Data
LSB MSB BIT
10
9
BYTE 3
11
6
12
BIT
5
291
BIT
4