MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 144

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

Clock Generator Module (CGM)
9.6.1 PLL Control Register (PCTL)
Technical Data
144
Addr.
$001C
$001D
$001E
NOTES:
1. When AUTO = 0, PLLIE is forced to logic zero and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic zero.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL Bandwidth Control
Register Name
PLL Control Register
PLL Programming
Register
Register
(PBWC)
(PCTL)
(PPG)
Address:
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Read:
Read:
Write:
Write:
Write:
Freescale Semiconductor, Inc.
Figure 9-4. CGM I/O Register Summary
For More Information On This Product,
$001C
PLLIE
AUTO
Bit 7
MUL7
PLLIE
Bit 7
0
0
0
0
Clock Generator Module (CGM)
Go to: www.freescale.com
Figure 9-5. PLL Control Register (PCTL)
= Unimplemented
= Unimplemented
LOCK
MUL6
PLLF
PLLF
6
0
0
1
6
0
PLLON
PLLON
MUL5
ACQ
5
1
0
1
5
1
MUL4
BCS
BCS
XLD
4
0
0
0
4
0
VRS7
3
1
1
0
0
0
3
1
1
MC68HC908AB32
VRS6
2
1
1
0
0
1
2
1
1
VRS5
1
1
1
0
0
1
1
1
1
MOTOROLA
—
Rev. 1.0
Bit 0
VRS4
Bit 0
1
1
0
0
0
1
1