MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 119

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

8.6.1 Interrupts
MC68HC908AB32
MOTOROLA
INTERRUPT
INTERRUPT
MODULE
MODULE
I-BIT
I-BIT
R/W
R/W
IDB
IDB
IAB
IAB
—
Rev. 1.0
DUMMY
DUMMY
At the beginning of an interrupt, the CPU saves the CPU register
contents onto the stack and sets the interrupt mask (I-bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
Figure 8-9
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt may take precedence, regardless of priority,
until the latched interrupt is serviced (or the I-bit is cleared).
(See
SP – 4
Freescale Semiconductor, Inc.
SP
Figure 8-9. Interrupt Recovery Timing
PC – 1[7:0] PC – 1[15:8]
For More Information On This Product,
Figure
Figure 8-8. Interrupt Entry Timing
CCR
SP – 1
SP – 3
System Integration Module (SIM)
shows interrupt recovery timing.
Go to: www.freescale.com
8-10.)
A
SP – 2
SP – 2
X
X
Figure 8-8
SP – 3
SP – 1
PC – 1[7:0] PC – 1[15:8] OPCODE
A
SP – 4
SP
shows interrupt entry timing, and
CCR
VECT H
PC
V DATA H
System Integration Module (SIM)
VECT L
PC + 1
OPERAND
V DATA L
START ADDR
Exception Control
OPCODE
Technical Data
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