MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 189

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908AB32
MOTOROLA
—
Rev. 1.0
Figure 11-11. TIMA Channel 2 Status and Control Register (TASC2)
Figure 11-12. TIMA Channel 3 Status and Control Register (TASC3)
Address:
Address:
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
Reset:
Reset:
Read:
Write:
Read:
Write:
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMA
counter registers matches the value in the TIMA channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading TIMA channel x status and control register with
CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic zero to CHxF has no effect. Therefore, an interrupt request
cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
$002C
$002F
CH2F
CH3F
Bit 7
Bit 7
0
0
0
0
Timer Interface Module A (TIMA)
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CH2IE
CH3IE
6
0
6
0
MS2B
5
0
5
0
0
MS2A
MS3A
4
0
4
0
ELS2B
ELS3B
3
0
3
0
Timer Interface Module A (TIMA)
ELS2A
ELS3A
2
0
2
0
TOV2
TOV3
1
0
1
0
Technical Data
I/O Registers
CH2MAX
CH3MAX
Bit 0
Bit 0
0
0
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