MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 87

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908AB32
MOTOROLA
NOTE:
—
Rev. 1.0
LVIPWRD — LVI Power Disable Bit
SSREC — Short Stop Recovery Bit
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
Extra care should be exercised when using this emulation part for
development of code to be run in ROM AB, AS or AZ parts that the
options selected by setting the CONFIG1 register match exactly the
options selected on any ROM code request submitted. The
enable/disable logic is not necessarily identical in all parts of the
AB, AS, and AZ families. If in doubt, check with your local field
applications representative.
LVIPWRD disables the LVI module. (See
Inhibit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 20. Computer Operating Properly
STOP enables the STOP instruction.
COPD disables the COP module. (See
Operating Properly
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = LVI module power disabled
0 = LVI module power enabled
1 = STOP mode recovery after 32 CGMXCLK cycles
0 = STOP mode recovery after 4096 CGMXCLK cycles
1 = COP timeout period is 2
0 = COP timeout period is 2
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
Configuration Register (CONFIG)
(LVI).)
Go to: www.freescale.com
(COP).)
18
13
– 2
– 2
4
4
CGMXCLK cycles
CGMXCLK cycles
Section 20. Computer
Configuration Register (CONFIG)
Section 21. Low-Voltage
(COP).)
Configuration Register 1
Technical Data
87