MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 237

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

14.8.2 ADC Data Register (ADR)
14.8.3 ADC Clock Register (ADCLK)
MC68HC908AB32
MOTOROLA
—
Rev. 1.0
Address:
Address:
One 8-bit result register, ADC data register (ADR), is provided. This
register is updated each time an ADC conversion completes.
The ADC clock register (ADCLK) selects the clock frequency for the
ADC.
ADIV[2:0] — ADC Clock Prescaler Bits
Reset:
Reset:
Read:
Write:
Read:
Write:
ADIV[2:0] form a 3-bit field which selects the divide ratio used by the
ADC to generate the internal ADC clock.
available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Freescale Semiconductor, Inc.
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ADIV2
Bit 7
AD7
Bit 7
Analog-to-Digital Converter (ADC)
0
0
Figure 14-5. ADC Clock Register (ADCLK)
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Figure 14-4. ADC Data Register (ADR)
= Unimplemented
= Unimplemented
ADIV1
AD6
6
0
6
0
ADIV0
AD5
5
0
5
0
ADICLK
AD4
4
0
4
0
AD3
3
0
3
0
0
Analog-to-Digital Converter (ADC)
Table 14-2
AD2
2
0
2
0
0
shows the
AD1
1
0
1
0
0
Technical Data
I/O Registers
Bit 0
AD0
Bit 0
0
0
0
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