HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 22

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

2.2
Read and write accesses to the DDR2 SDRAM are
burst oriented; accesses start at a selected location
and continue for the burst length of four or eight in a
programmed sequence.
Accesses begin with the registration of an Activate
command, which is followed by a Read or Write
command. The address bits registered coincident with
the activate command are used to select the bank and
row to be accessed. BA[1:0] select the bank, A[13:0]
2.2.1
DDR2 SDRAM’s must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below
2. Start clock (CK, CK) and maintain stable power and
3. Apply NOP or Deselect commands and take CKE
4. Wait minimum of 400 ns, then issue a Precharge-all
5. Issue EMRS(2) command. To issue EMRS(2)
Data Sheet
0.2
may be undefined). To guarantee ODT off,
must be valid and a low level must be applied to the
ODT pin. Maximum power up interval for
is specified as 10.0 ms. The power interval is
defined as the amount of time it takes for
to power-up from 0 V to 1.8 V
one of these two sets of conditions must be met:
–
–
–
– Apply
– Apply
– Apply
clock condition
high.
command.
command, provide “low” to BA0 and “high” to BA1.
or
V
power converter output, AND
V
V
V
DD
TT
ref
ref
V
.
,
is limited to 0.95 V max, AND
tracks
DDQ
V
V
V
V
Basic Functionality
Power On and Initialization
DDL
DD
DDL
DDQ
and ODT at a low state (all other inputs
V
before or at the same time as
and
before or at the same time as
before or at the same time as
DDQ
for a minimum of 200 µs.
/2
V
DDQ
are driven from a single
±
100 mV. At least
.
V
V
DD
DD
V
V
V
/
/
REF
DDL
V
V
V
DDQ
TT
DDQ
DDQ
.
.
&
22
select the row for 4 and 8 components, A[12:0] select
the row for 16 components.
The address bits registered coincident with the Read or
Write command are used to select the starting column
location for the burst access and to determine if the
Auto-Precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register
definition, command description and device operation.
6. Issue EMRS(3) command. To issue EMRS(3)
7. Issue EMRS(1) to enable DLL. To issue “DLL
8. Issue a MRS command for “DLL reset”. To issue
9. Issue Precharge-all command.
10. Issue 2 or more Auto-refresh commands.
11. Issue a MRS command with low on A8 to initialize
12. At least 200 clocks after step 8, execute Off Chip
13. The DDR2 SDRAM is now ready for normal
512-Mbit Double-Data-Rate-Two SDRAM
command, provide “high” to BA[1:0].
Enable” command, provide “low” to A0 and “high” to
BA0 and “low” to BA1 and A13.
DLL reset command, provide “high” to A8 and “low”
to BA[1:0] and A13.
device operation (i.e. to program operating
parameters without resetting the DLL.)
Driver impedance adjustment ( OCD Calibration). If
OCD calibration is not used, EMRS OCD Default
command (A9 = A8 = A7 = 1) followed by EMRS
OCD Calibration Mode Exit command
(A9 = A8 = A7 = 0) must be issued with other
operating parameters of EMRS(1).
operation.
HYB18T512[400/800/160]A[C/F]–[3.7/5]
Functional Description
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05