HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 30

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

For proper operation of adjust mode, WL = RL - 1 =
AL + CL - 1 clocks and
Figure
Figure 10
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for
controllers to measure DDR2 SDRAM Driver
impedance before OCD impedance adjustment. In this
mode, all outputs are driven out
Figure 11
Data Sheet
DQS_in
DQS_in
CK, CK
CMD
DQ_in
CK, CK
CMD
DQ_in
DM
10. Input data pattern for adjustment, DT[0:3] is
EMRS(1)
EMRS(1)
Timing Diagram Adjust Mode
Timing Diagram Drive Mode
tOIT
OCD adjust mode
Enter Drive Mode
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0
WL
t
NOP
NOP
DS
/
t
DH
tDS tDH
should be met as
t
DT0
OIT
NOP
NOP
after “enter drive
DQS high for Drive(1)
DQS high for Drive(0)
DT1
DQS
DT2
NOP
NOP
DT3
30
NOP
NOP
fixed and not affected by MRS addressing mode (i.e.
sequential or interleave).
Burst length of 4 have to be programmed in the MRS for
OCD impedance adjustment.
mode” command and all output drivers are turned-off
t
Figure
OIT
512-Mbit Double-Data-Rate-Two SDRAM
after “OCD calibration mode exit” command. See
HYB18T512[400/800/160]A[C/F]–[3.7/5]
11.
EMRS(1)
NOP
tOIT
OCD calibration
OCD calibration
mode exit
tWR
mode exit
NOP
NOP
EMRS(1)
Functional Description
NOP
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05
NOP
NOP
OCD1
OCD2