HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 7

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

1
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its
main characteristics.
1.1
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
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Table 1
Product Type Speed Code
Speed Grade
max. Clock Frequency
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
1.2
The 512-Mb DDR2 DRAM is a high-speed Double-
Data-Rate-2 CMOS Synchronous DRAM device
containing 536,870,912 bits and internally configured
as a quad-bank DRAM. The 512-Mb device is
organized as either 32 Mbit
8 I/O
synchronous devices achieve high speed transfer rates
starting at 400 Mb/sec/pin for general applications. See
Table 1
The device is designed to comply with all DDR2 DRAM
key features:
Data Sheet
1.8 V
1.8 V
DRAM organisations with 4, 8 and 16 data
in/outputs
Double Data Rate architecture: two data transfers
per clock cycle, four internal banks for concurrent
operation
CAS Latency: 3, 4 and 5
Burst Length: 4 and 8
Differential clock inputs (CK and CK)
Bi-directional, differential data strobes (DQS and
DQS) are transmitted / received with data. Edge
aligned with read data and center-aligned with write
data.
DLL aligns DQ and DQS transitions with clock
DQS can be disabled for single-ended data strobe
operation
4 bank or 8 Mbit
for performance figures.
±
±
0.1 V Power Supply
0.1 V (SSTL_18) compatible I/O
Overview
Features
High Performance
Description
16 I/O
4 I/O
4 bank chip. These
@CL5
@CL4
@CL3
4 bank, 16 Mbit
f
f
f
t
t
t
t
CK5
CK4
CK3
RCD
RP
RAS
RC
–3.7
DDR2–533 4–4–4
266
266
200
15
15
45
60
7
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1. posted CAS with additive latency,
2. write latency = read latency - 1,
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment and
5. an On-Die Termination (ODT) function.
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential
clocks (CK rising and CK falling). All I/Os are
synchronized with a single ended DQS or differential
DQS-DQS pair in a source synchronous fashion.
512-Mbit Double-Data-Rate-Two SDRAM
Commands entered on each positive clock edge,
data and data mask are referenced to both edges of
DQS
Data masks (DM) for write data
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver impedance adjustment (OCD) and
On-Die-Termination (ODT) for better signal quality.
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving
Power-Down modes
Average Refresh Period 7.8 s at a
than 85 °C, 3.9 s between 85 °C and 95 °C
Normal and Weak Strength Data-Output Drivers
1K page size for 4 & 8, 2K page size for 16
Packages:
P-TFBGA-60-6 for 4 & 8 components
P-TFBGA-84-1 for 16 components
HYB18T512[400/800/160]A[C/F]–[3.7/5]
–5
DDR2–400 3–3–3
200
200
200
15
15
40
55
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05
T
CASE
Overview
lower
Units
—
MHz
MHz
MHz
ns
ns
ns
ns