HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 26

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

Field
OCD
Program
DQS
RDQS
Qoff
1) w = write only register bits
A0 is used for DLL enable or disable. A1 is used for
enabling half-strength data-output driver. A2 and A6
enables ODT (On-Die termination) and sets the Rtt
value. A[5:3] are used for additive latency settings and
A[9:7] enables the OCD impedance adjustment mode.
A10 enables or disables the differential DQS and
RDQS signals, A11 disables or enables RDQS.
Address bit A12 have to be set to “low” for normal
Single-ended and Differential Data Strobe Signals
Table 8
RDQS, RQDS which can be programmed by A[11:10]
address bits in EMRS. RDQS and RDQS are available
in 8 components only.
Table 8
EMRS(1)
A11
(RDQS Enable)
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
DLL Enable/Disable
Data Sheet
lists all possible combinations for DQS, DQS,
Bits
[9:7]
10
11
12
Single-ended and Differential Data Strobe Signals
A10
(DQS Enable)
0 (Enable)
1 (Disable)
0 (Enable)
1 (Disable)
Type
w
w
w
w
1)
Description (cont’d)
Off-Chip Driver Calibration Program
Every calibration mode command should be followed by “OCD calibration mode exit”
before any other command will be issued; see
000 OCD calibration mode exit, maintain setting
001 Drive 1
010 Drive 0
100 Adjust mode
111 OCD calibration default
Complement Query Strobe (DQS, RDQS Output)
If enabled the complement query strobe (DQS output) is driven high one clock cycle
before valid query data (DQ) is driven onto the data bus; see
0
1
Read Data Strobe Output (RDQS, RDQS)
0
1
Output Disable
Disabling the DRAM outputs (DQ, DQS, DQS, RDQS, RDQS) allows users to
measure
0
1
Output buffers enabled
Note: When Adjust Mode is issued, AL from previously set value must be applied.
Note: After setting to default, OCD mode needs to be exited by setting A[9:7] to 000.
Enable
Disable
Disable
Enable
Output buffers disabled
Strobe Function Matrix
RDQS/DM
DM
DM
RDQS
RDQS
I
DD
during Read operations without including the output buffer current.
RDQS
Hi-Z
Hi-Z
RDQS
Hi-Z
26
operation. With A12 set to “high” the SDRAM outputs
are disabled and in Hi-Z. “High” on BA0 and “low” for
BA1 have to be set to access the EMRS(1). A13 and all
“higher” address bits have to be set to “low” for
compatibility with other DDR2 memory products with
higher memory densities. Refer to
Definition (BA[1:0] = 00
If RDQS is enabled in 8 components, the DM function
is disabled. RDQS is active for reads and don’t care for
writes.
DQS
DQS
DQS
DQS
DQS
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512[400/800/160]A[C/F]–[3.7/5]
DQS
DQS
Hi-Z
DQS
Hi-Z
Chapter
Signaling
differential DQS signals
single-ended DQS signals
differential DQS signals
single-ended DQS signals
2.3.
B
).
Functional Description
Chapter
09112003-SDM9-IQ3P
Mode Register
Rev. 1.13, 2004-05
2.6.3.