HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 42

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

Figure 27
The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
Figure 28
The seamless, non interrupting 8-bit read operation is supported by enabling a read command at every BL/2
number of clocks. This operation is allowed regardless of same or different banks as long as the banks are
activated.
2.6.4
The Write command is initiated by having CS, CAS and
WE low while holding RAS high at the rising edge of the
clock. The address inputs determine the starting
column address. Write latency (WL) is defined by a
read latency (RL) minus one and is equal to (AL + CL -
1). A data strobe signal (DQS) has to be driven low
(preamble) a time
bit of the burst cycle must be applied to the DQ pins at
the first rising edge of the DQS following the preamble.
The
cycles. The subsequent burst bit data are issued on
Data Sheet
DQS,
DQS
CK, CK
CMD
CK, CK
DQ
DQS,
DQS
DQ
CMD
t
DQSS
Post CAS
READ A
T
0
Post CAS
READ A
T
0
specification must be satisfied for write
Seamless Read Operation Example: RL = 5, AL = 2, CL = 3, BL = 4
Seamless Read Operation Example: RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)
Write Command
T
1
NOP
AL = 2
t
T
1
WPRE
CL = 3
RL = 3
NOP
prior to the WL. The first data
T
2
NOP
Post CAS
T
2
READ B
RL = 5
T
3
NOP
Dout A0
CL = 3
T
3
Dout A1
NOP
Post CAS
T
4
READ B
Dout A2
Dout A3
T
4
NOP
T
5
NOP
Dout A4
42
Dout A5
successive edges of the DQS until the burst length is
completed. When the burst has finished, any additional
data supplied to the DQ pins will be ignored. The DQ
signal is ignored after the burst write operation is
complete. The time from the completion of the burst
write to bank precharge is named “write recovery time”
(
the memory array.
(see
programmed value for WR in the MRS.
T
5
T
6
t
NOP
Dout A0
WR
NOP
Dout A4
512-Mbit Double-Data-Rate-Two SDRAM
) and is the time needed to store the write data into
AC & DC Operating
HYB18T512[400/800/160]A[C/F]–[3.7/5]
Dout A1
Dout A7
T
7
T
6
NOP
Dout B0
NOP
Dout A2
Dout B1
Dout A3
T
8
NOP
t
Dout B2
WR
T
7
NOP
Dout B0
SBR_BL8
is an analog timing parameter
Dout B3
T
9
Conditions) and is not the
Dout B1
NOP
Dout B4
T
8
Functional Description
NOP
09112003-SDM9-IQ3P
Dout B5
Dout B2
T10
Rev. 1.13, 2004-05
NOP
Dout B6
Dout B3
SBR523
Dout B7
NOP