HYB18T512160AC-37 INFINEON [Infineon Technologies AG], HYB18T512160AC-37 Datasheet - Page 27

• Manufacturer Part Number: HYB18T512160AC-37
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

The DLL must be enabled for normal operation. DLL
enable is required during power up initialization, and
upon returning to normal operation after having the DLL
disabled. The DLL is automatically disabled when
entering Self-Refresh operation and is automatically re-
enabled upon exit of Self-Refresh operation. Any time
Output Disable (Qoff)
Under normal operation, the DRAM outputs are
enabled during Read operation for driving data (Qoff bit
in the EMRS(1) is set to 0). When the Qoff bit is set to
1, the DRAM outputs will be disabled. Disabling the
2.2.4
The Extended Mode Registers EMRS(2) and EMRS(3)
are reserved for future use and must be programmed
when setting the mode register during initialization.
The extended mode register(2) controls refresh related
features. The default value of the extended mode reg-
ister(2) is not defined, therefore the extended mode
register(2) must be written after Power-up for proper
operation.
The extended mode register EMRS(2) is written by
asserting low on CS, RAS, CAS, WE, BA0 and high on
EMRS(2) Programming
Extended Mode Register Definition
1) A13 is only available for 4 and 8 configuration.
2) Must be programmed to “0”
2.2.5
The Extended Mode Register EMRS(3) is reserved for
future use and all bits except BA0 and BA1 must be
EMRS(3) Programming
Extended Mode Register Definition
1) A13 is only available for 4 and 8 configuration.
2) Must be programmed to “0”
Data Sheet
BA1
BA1
1
1
BA0
BA0
0
1
EMRS(2)
EMRS(3)
A13
A13
A12
A12
A11
A11
A10
A10
A9
A9
(BA[1:0] = 01
(BA[1:0] = 01
A8
A8
reg. addr
reg.addr
27
the DLL is enabled (and subsequently reset), 200 clock
cycles must occur before a Read command can be
issued to allow time for the internal clock to be
synchronized with the external clock. Failing to wait for
synchronization to occur may result in a violation of the
t
DRAM outputs allows users to measure IDD currents
during Read operations, without including the output
buffer current.
BA1,while controlling the states of the address pins.
The DDR2 SDRAM should be in all bank precharge
with CKE already high prior to writing into the extended
mode register(2). The mode register set command
cycle time (
operation to the extended mode register(2). Mode
register contents can be changed using the same
command and clock cycle requirements during normal
operation as long as all banks are in precharge state.
programmed to 0 when setting the mode register during
initialization.
A7
A7
AC
512-Mbit Double-Data-Rate-Two SDRAM
or
0
0
B
B
1)2)
1)2)
HYB18T512[400/800/160]A[C/F]–[3.7/5]
)
)
t
DQSCK
A6
A6
t
MRD
parameters.
A5
A5
) must be satisfied to complete the write
A4
A4
A3
A3
Functional Description
09112003-SDM9-IQ3P
Rev. 1.13, 2004-05
A2
A2
A1
A1
A0
A0