AGL015 MICROSEMI [Microsemi Corporation], AGL015 Datasheet - Page 108

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AGL015

Manufacturer Part Number
AGL015
Description
IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
Manufacturer
MICROSEMI [Microsemi Corporation]
Datasheet

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Manufacturer
Quantity
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Manufacturer:
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IGLOO DC and Switching Characteristics
Figure 2-20 • Output Enable Register Timing Diagram
Table 2-161 • Output Enable Register Propagation Delays
2- 92
Enable
CLK
D_Enable
Preset
EOUT
Clear
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OECLKQ
OESUD
OEHD
OESUE
OEHE
OECLR2Q
OEPRE2Q
OEREMCLR
OERECCLR
OEREMPRE
OERECPRE
OEWCLR
OEWPRE
OECKMPWH
OECKMPWL
For specific junction temperature and voltage supply levels, refer to
Output Enable Register
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
Clock Minimum Pulse Width High for the Output Enable Register
Clock Minimum Pulse Width Low for the Output Enable Register
50%
1.5 V DC Core Voltage
50%
t
OESUE
1
t
OEHE
50%
t
OESUD
50%
t
OECLKQ
0
t
50%
OEHD
50%
50%
t
OEWPRE
J
t
OEPRE2Q
= 70°C, Worst-Case VCC = 1.425 V
50%
Description
50%
t
R ev i sio n 1 9
50%
OERECPRE
50%
t
t
OEWCLR
OECLR2Q
50%
50%
Table 2-6 on page 2-7
t
50%
OERECCLR
50%
t
OECKMPWH
t
OEREMPRE
50%
for derating values.
50%
t
OECKMPWL
0.75
0.51
0.00
0.73
0.00
1.13
1.13
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std. Units
t
OEREMCLR
50%
50%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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