AGL015 MICROSEMI [Microsemi Corporation], AGL015 Datasheet - Page 131

• Manufacturer Part Number: AGL015
• Description: IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
• Manufacturer: MICROSEMI [Microsemi Corporation]

Clock Conditioning Circuits
Table 2-189 • IGLOO CCC/PLL Specification
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL
Input Cycle-to-Cycle Jitter (peak magnitude)
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
CCC Output Peak-to-Peak Period Jitter F
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
4. The AGL030 device does not support a PLL.
5. Maximum value obtained for a Std. speed grade device in Worst-Case Commercial Conditions. For specific junction
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
7. Measurements done with LVTTL 3.3 V, 8 mA I/O drive strength, and high slew Rate. VCC/VCCPLL = 1.14 V, VQ/PQ/TQ
8. Switching I/Os are placed outside of the PLL bank.
increments are available. Refer to SmartGen online help for more information.
temperature and voltage supply levels, refer to
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
type of packages, 20 pF load.
0.75 MHz to 50 MHz
50 MHz to 160 MHz
J
= 25°C, V
CCC Electrical Specifications
Timing Characteristics
For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage
5
CC
= 1.5 V
1, 2
4,5
CCC_OUT
IN_CCC
1,2
1,2
OUT_CCC
Table 2-6 on page 2-7
1, 2
Table 2-6 on page 2-7
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
R ev i si o n 1 9
for derating values.
SSO ≥ 4
Maximum Peak-to-Peak Jitter Data
0.60%
4.00%
0.469
Min.
0.75
1.25
and
48.5
1.5
Table 2-7 on page 2-7
IGLOO Low Power Flash FPGAs
SSO ≥ 8 SSO ≥ 16
0.80%
6.00%
360
Typ.
3.5
3
12.00%
1.20%
15.65
15.65
Max.
250
250
100
300
51.5
6.0
2.5
1.5
32
1
for deratings.
Units
MHz
MHz
ms
ps
ns
ns
µs
ns
ns
ns
ns
ns
%
7.8
2- 115