AGL015 MICROSEMI [Microsemi Corporation], AGL015 Datasheet - Page 152

• Manufacturer Part Number: AGL015
• Description: IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
• Manufacturer: MICROSEMI [Microsemi Corporation]

Pin Descriptions
JTAG Pins
3- 4
IGLOO devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any
voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate,
even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must
be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate
I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the
JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be
tied to GND.
TCK
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-
up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor
placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements. Refer to
Table 3-2
Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins
Table 3-3 • TRST and TCK Pull-Down Recommendations
TDI
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor
on the TDI pin.
TDO
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an
internal weak pull-up resistor on the TMS pin.
TRST
The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-
down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor
values must be chosen from
values in
equivalent parallel resistor when multiple devices are connected via a JTAG chain.
VJTAG
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Notes:
1. The TCK pin can be pulled-up or pulled-down.
2. The TRST pin is pulled-down.
3. Equivalent parallel resistance if more than one device is on the JTAG chain
VJTAG
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Note:
Equivalent parallel resistance if more than one device is on the JTAG chain
for more information.
Table 3-2
correspond to the resistor recommended when a single device is used, and the
Test Clock
Test Data Input
Test Data Output
Test Mode Select
Boundary Scan Reset Pin
Table 3-2
and must satisfy the parallel resistance value requirement. The
R ev isio n 1 9
Tie-Off Resistance
Tie-Off Resistance*
200 Ω to 1 kΩ
200 Ω to 1 kΩ
500 Ω to 1 kΩ
500 Ω to 1 kΩ
200 Ω to 1 kΩ
200 Ω to 1 kΩ
500 Ω to 1 kΩ
500 Ω to 1 kΩ
1,2