AGL015 MICROSEMI [Microsemi Corporation], AGL015 Datasheet - Page 11

• Manufacturer Part Number: AGL015
• Description: IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
• Manufacturer: MICROSEMI [Microsemi Corporation]

Figure 1-3 • IGLOO Flash*Freeze Mode
Figure 1-4 • VersaTile Configurations
X1
X2
X3
LUT-3 Equivalent
LUT-3
Flash*Freeze Technology
The IGLOO device has an ultra-low power static mode, called Flash*Freeze mode, which retains all
SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology
enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global
I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be
driven or can be toggling without impact on power consumption, and the device retains all core registers,
SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a
certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the
I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as 5 µW in this mode.
Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if
Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low power
static (as low as 12 µW) and dynamic capabilities of the IGLOO device. Refer to
illustration of entering/exiting Flash*Freeze mode.
VersaTiles
The IGLOO core consists of VersaTiles, which have been enhanced beyond the ProASIC
tiles. The IGLOO VersaTile supports the following:
Refer to
•
•
•
•
Y
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Figure 1-4
Mode Control
Flash*Freeze
for VersaTile configurations.
D-Flip-Flop with Clear or Set
Data
CLK
CLR
D-FF
R ev i si o n 1 9
Flash*Freeze Pin
Y
IGLOO FPGA
Enable D-Flip-Flop with Clear or Set
Enable
Data
CLK
CLR
IGLOO Low Power Flash FPGAs
D-FF
Figure 1-3
Y
PLUS®
for an
core
1 -5