AGL015 MICROSEMI [Microsemi Corporation], AGL015 Datasheet - Page 99

• Manufacturer Part Number: AGL015
• Description: IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
• Manufacturer: MICROSEMI [Microsemi Corporation]

Figure 2-14 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
Figure 2-15 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-151 • Minimum and Maximum DC Input and Output Levels
DC Parameter
VCCI
VOL
OUTBUF_LVPECL
R
T
Z
Z
Z
0
0
stub
Receiver
+
R
R
S
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to
high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain
any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive
current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series
terminations for better signal quality and to control voltage swing. Termination is also required at both
ends of the bus since the driver can be located anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.
Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20
loads. A sample application is given in
the LVDS section in
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required
differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R
R
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
-
T
EN
R
Z
= 70 Ω, given Z
S
stub
Supply Voltage
Output Low Voltage
FPGA
Z
Z
Z
0
0
stub
Transceiver
+
R
T
S
0
Description
-
Table 2-149 on page 2-82
= 50 Ω (2") and Z
N
EN
P
R
Z
stub
S
Bourns Part Number: CAT16-PC4F12
Z
Z
100 Ω
100 Ω
Z
0
0
stub
Driver
+
R
D
S
stub
-
EN
R
Figure
Z
S
stub
187 W
= 50 Ω (~1.5").
R ev i si o n 1 9
and
2-14. The input and output buffer delays are available in
Z
Z
Z
Z
Z
0
0
0
0
Min.
stub
0.96
= 50 Ω
= 50 Ω
Table 2-150 on page
Receiver
+
3.0
R
R
S
Max.
-
1.27
EN
R
100 Ω
Z
S
stub
Min.
1.06
...
N
P
3.3
IGLOO Low Power Flash FPGAs
2-82.
Max.
1.43
Z
Z
0
0
FPGA
Transceiver
+
–
+
R
T
Min.
1.30
S
-
INBUF_LVPECL
EN
R
3.6
S
Figure
Max.
1.57
S
BIBUF_LVDS
= 60 Ω and
Z
Z
2-15. The
0
0
Units
V
V
2- 83
R
T