AGL015 MICROSEMI [Microsemi Corporation], AGL015 Datasheet - Page 57

• Manufacturer Part Number: AGL015
• Description: IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
• Manufacturer: MICROSEMI [Microsemi Corporation]

Table 2-47 • Minimum and Maximum DC Input and Output Levels
Table 2-48 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
3.3 V LVTTL /
3.3 V LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
3. Currents are measured at 100°C junction temperature and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
larger when operating outside recommended ranges.
larger when operating outside recommended ranges
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V
software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a specification.
Applicable to Advanced I/O Banks
Applicable to Standard Plus I/O Banks
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
V
VIL
VIL
Max.
Max.
0.8
0.8
0.8
0.8
0.8
0.8
V
0.8
0.8
0.8
0.8
0.8
0.8
0.8
V
Min.
Min.
V
2
2
2
2
2
2
V
2
2
2
2
2
2
2
VIH
VIH
Max.
Max.
3.6
3.6
3.6
3.6
3.6
3.6
V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
Max.
V
Max.
0.4
0.4
0.4
0.4
0.4
0.4
VOL
V
OL
0.4
0.4
0.4
0.4
0.4
0.4
0.4
R ev i si o n 1 9
V
VOH
Min.
2.4
2.4
2.4
2.4
2.4
2.4
VOH
Min.
V
2.4
2.4
2.4
2.4
2.4
2.4
2.4
V
IOL IOH
mA mA
12
16
2
4
6
IOL IOH
mA mA
8
24 24
12 12
16 16
2
6
4
8
12
16
2
6
4
8
2
6
4
8
IGLOO Low Power Flash FPGAs
IOSL
Max.
mA
IOSL
Max.
mA
103
103
103
132
268
25
25
51
51
25
25
51
51
3
3
IOSH
Max.
mA
IOSH
Max.
109
109
mA
109
27
27
54
54
127
181
27
27
54
54
3
3
µA
IIL
µA
IIL
10
10
10
10
10
10
10
10
10
10
10
10
10
1
4
1
4
IIH
µA
IIH
µA
10
10
2- 41
10
10
10
10
10
10
10
10
10
10
10
2
4
2
4