AGL015 MICROSEMI [Microsemi Corporation], AGL015 Datasheet - Page 149

• Manufacturer Part Number: AGL015
• Description: IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
• Manufacturer: MICROSEMI [Microsemi Corporation]

3 – Pin Descriptions
Supply Pins
GND
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always
be connected to GND on the board.
VCC
Supply voltage to the FPGA core, nominally 1.5 V for IGLOO V5 devices, and 1.2 V or 1.5 V for IGLOO
V2 devices. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a
device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain
powered to allow JTAG signals to pass through the device.
For IGLOO V2 devices, VCC can be switched dynamically from 1.2 V to 1.5 V or vice versa. This allows
in-system programming (ISP) when VCC is at 1.5 V and the benefit of low power operation when VCC is
at 1.2 V.
VCCIBx
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to
eight I/O banks on IGLOO devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI
connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V, 1.5 V, 1.8 V, 2.5 V,
or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND.
VMVx
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the
VMV plane is decoupled from the simultaneous switching noise originating from the output buffer VCCI
domain. This minimizes the noise transfer within the package and improves input signal integrity. Each
bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank
run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each
I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have
their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given
I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e.,
VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLA/B/C/D/E/F
Supply voltage to analog PLL, nominally 1.5 V or 1.2 V.
When the PLLs are not used, the Microsemi Designer place-and-route tool automatically disables the
unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to
ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple
VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning
Circuits in Low Power Flash Devices and Mixed Signal FPGAs" chapter of the
User’s Guide
VCOMPLA/B/C/D/E/F
Ground to analog PLL power supplies. When the PLLs are not used, the Microsemi Designer place-and-
route tool automatically disables the unused PLLs to lower power consumption. The user should tie
unused VCCPLx and VCOMPLx pins to ground.
There is one VCOMPLF pin on IGLOO devices.
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1.5 V for IGLOO V5 devices
1.2 V or 1.5 V for IGLOO V2 devices
There is one VCCPLF pin on IGLOO devices.
for a complete board solution for the PLL analog power supply and ground.
Ground
Core Supply Voltage
I/O Supply Voltage
I/O Supply Voltage (quiet)
Ground (quiet)
PLL Supply Voltage
PLL Ground
R ev i si o n 1 9
IGLOO FPGA Fabric
3 -1