NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 19

• Manufacturer Part Number: NT5DS16M16CS
• Description: 256Mb DDR Synchronous DRAM
• Manufacturer: NANOAMP [NanoAmp Solutions, Inc.]

NanoAmp Solutions, Inc.
Operations
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened”
(activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row
in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active
command), a Read or Write command may be issued to that row, subject to the t
mand to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The
minimum time interval between successive Active commands to the same bank is defined by t
mand to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access
overhead. The minimum time interval between successive Active commands to different banks is defined by t
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
Activating a Specific Row in a Specific Bank
BA0, BA1
A0-A12
CKE
RAS
CAS
WE
CK
CK
CS
HIGH
RA
BA
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
RA = row address.
BA = bank address.
RCD
specification. A subsequent Active com-
Don’t Care
RC
. A subsequent Active com-
RRD
.
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