NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 26

• Manufacturer Part Number: NT5DS16M16CS
• Description: 256Mb DDR Synchronous DRAM
• Manufacturer: NANOAMP [NanoAmp Solutions, Inc.]

NanoAmp Solutions, Inc.
Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled Terminating a
Read Burst: CAS Latencies (Burst Length = 8) on page 27. The Burst Terminate latency is equal to the read (CAS) latency, i.e.
the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data
element pairs.
Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is
necessary, the Burst Terminate command must be used, as shown in timing figure entitled Read to Write: CAS Latencies (Burst
Length = 4 or 8) on page 28. The example is shown for t
time. t
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge
was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of
desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure Read to Pre-
charge: CAS Latencies (Burst Length = 4 or 8) on page 29 for Read latencies of 2 and 2.5. Following the Precharge command,
a subsequent command to the same bank cannot be issued until t
during the access of the last data elements.
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above)
provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the
Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the
command. The advantage of the Precharge command is that it can be used to truncate bursts.
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
DQSS
(min) and t
DQSS
(max) are defined in the section on Writes.
DQSS
(min). The t
RP
is met. Note that part of the row precharge time is hidden
DQSS
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
(max) case, not shown here, has a longer bus idle
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