DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet - Page 16

• Manufacturer Part Number: DS2153QN-A7/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2153QN-A7/T&R

• Product: Framer
• Number Of Transceivers: 1
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.8 V
• Part # Aliases: 90-2153Q-NT7

CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)
(MSB)
TESE
SYMBOL
TSCLKM
TCBFS
LIRST
TIRFS
TESE
ESR
—
—
TCBFS
POSITION
CCR3.7
CCR3.6
CCR3.5
CCR3.4
CCR3.3
CCR3.2
CCR3.1
CCR3.0
TIRFS
NAME AND DESCRIPTION
Transmit Elastic Store Enable.
0 = elastic store is disabled
1 = elastic store is enabled
Transmit Channel Blocking Registers (TCBR) Function
Select.
0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
Transmit Idle Registers (TIR) Function Select.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER
Elastic Stores Reset. Setting this bit from a 1 to a 0 will force
the elastic stores to a known depth. Should be toggled after
SYSCLK has been applied and is stable. Must be set and cleared
again for a subsequent reset. Do not leave this bit set high.
Line Interface Reset. Setting this bit from a 0 to a 1 will initiate
an internal reset that affects the slicer, AGC, clock recovery state
machine, and jitter attenuator. Normally this bit is only toggled
on power-up. Must be cleared and set again for a subsequent
reset.
Not Assigned. Should be set to 0 when written.
Transmit Backplane Clock Select. Must be set like RCR2.2.
0 = 1.544MHz
1 = 2.048MHz
Not Assigned. Should be set to 0 when written.
ESR
16 of 60
LIRST
—
TSCLKM
(LSB)
—