DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet - Page 35

• Manufacturer Part Number: DS2153QN-A7/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2153QN-A7/T&R

• Product: Framer
• Number Of Transceivers: 1
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.8 V
• Part # Aliases: 90-2153Q-NT7

DS2153Q
11 ELASTIC STORES OPERATION
The DS2153Q has an on-board two-frame (512 bits) elastic store. This elastic store can be enabled via
RCR2.1. If the elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544MHz
(RCR2.2 = 0) or 2.048MHz (RCR2.2 = 1) clock at the SYSCLK pin. If the elastic store is enabled, then
the user has the option of either providing a frame sync at the RSYNC pin (RCR1.5 = 1) or having the
RSYNC pin provide a pulse on frame or multiframe boundaries (RCR1.5 = 0). If the user wishes to
obtain pulses at the frame boundary, then RCR1.6 must be set to 0, and if the user wishes to have pulses
occur at the multiframe boundary, then RCR1.6 must be set to 1. If the user selects to apply a 1.544MHz
clock to the SYSCLK pin, then every fourth channel will be deleted and the F-bit position inserted
(forced to 1). Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) will
be deleted. Also, in 1.544MHz applications, the RCHBLK output will not be active in channels 25
through 32 (or in other words, RCBR4 is not active). See Section
14
for more details. If the 512-bit
elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of
data (256 bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to 1. If the buffer fills,
then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to 1.
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