DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet - Page 9

• Manufacturer Part Number: DS2153QN-A7/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2153QN-A7/T&R

• Product: Framer
• Number Of Transceivers: 1
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.8 V
• Part # Aliases: 90-2153Q-NT7

DS2153Q
3 PARALLEL PORT
The DS2153Q is controlled via a multiplexed bidirectional address/data bus by an external
microcontroller or microprocessor. The DS2153Q can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in Section
14
for more details. The multiplexed bus on the DS2153Q saves pins because the address information and
data information share the same signal paths. The addresses are presented to the pins in the first portion of
the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses
must be valid prior to the falling edge of ALE (AS), at which time the DS2153Q latches the address from
the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS
or
pulses. In a read cycle, the DS2153Q outputs a byte of data during the latter portion of the DS or
WR
pulses. The read cycle is terminated and the bus returns to a high-impedance state as
transitions
RD
RD
high in Intel timing or as DS transitions low in Motorola timing.
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