DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet - Page 33

• Manufacturer Part Number: DS2153QN-A7/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2153QN-A7/T&R

• Product: Framer
• Number Of Transceivers: 1
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.8 V
• Part # Aliases: 90-2153Q-NT7

10 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel
Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins,
respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either
high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD
controller in ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing diagrams in
Section
the option to use the TCBRs to determine on a channel by channel basis, which signaling bits are to be
inserted via the TSRs (the corresponding bit in the TCBRs = 1) and which are to be sourced from the
TSER pin (the corresponding bit in the TCBR = 0). See the Transmit Data Flow diagram in Section
for more details.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING
REGISTERS (Address = 2B to 2E Hex)
TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING
REGISTERS (Address = 22 to 25 Hex)
Note: If CCR3.6 = 1, then a 0 in the TCBRs implies that signaling data is to be sourced from TSER and a 1 implies that signaling data for
that channel is to be sourced from the Transmit Signaling (TS) registers.
(MSB)
(MSB)
CH16
CH24
CH32
CH16
CH24
CH32
CH8
CH8
SYMBOL
SYMBOL
14
CH32
CH32
CH1
CH1
for an example. The TCBRs have an alternate mode of use. Via the CCR3.6 bit, the user has
CH15
CH23
CH31
CH7
CH15
CH23
CH31
CH7
CH14
CH22
CH30
CH6
CH14
CH22
CH30
CH6
POSITION
POSITION
RCBR4.7
RCBR1.0
TCBR4.7
TCBR1.0
CH13
CH21
CH29
CH5
CH13
CH21
CH29
CH5
NAME AND DESCRIPTION
Receive Channel Blocking Registers.
0 = force the RCHBLK pin to remain low during this
channel time
1 = force the RCHBLK pin high during this channel time
NAME AND DESCRIPTION
Transmit Channel Blocking Registers.
0 = force the TCHBLK pin to remain low during this
channel time
1 = force the TCHBLK pin high during this channel time
CH12
CH20
CH28
CH4
CH12
CH20
CH28
33 of 60
CH4
CH11
CH19
CH27
CH11
CH19
CH27
CH3
CH3
CH10
CH18
CH26
CH10
CH18
CH26
CH2
CH2
(LSB)
CH17
CH25
(LSB)
CH17
CH25
CH1
CH9
CH1
CH9
RCBR1 (2B)
RCBR2 (2C)
RCBR3 (2D)
RCBR4 (2E)
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)
14