DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet - Page 7

• Manufacturer Part Number: DS2153QN-A7/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2153QN-A7/T&R

• Product: Framer
• Number Of Transceivers: 1
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.8 V
• Part # Aliases: 90-2153Q-NT7

21, 22
25, 26
PIN
20
23
24
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TCHBLK
TCHCLK
XTAL1,
TSYNC
XTAL2
TLCLK
NAME
RRING
TRING
TLINK
DVDD
RVDD
TVDD
TCLK
RVSS
TVSS
RTIP,
TSER
TTIP
BTS
INT1
INT2
TYPE
I/O
—
—
—
—
—
—
—
—
—
O
O
O
O
O
I
I
I
I
Bus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the
ALE(AS), and
function listed in parentheses ().
Receive Tip and Ring. Analog inputs for clock recovery circuitry;
connects to a 1:1 transformer (see Section
Receive Analog Positive Supply. 5.0V. Should be tied to DVDD and
TVDD pins.
Receive Signal Ground. 0V. Should be tied to local ground plane.
Crystal Connections. A pullable 8.192MHz crystal must be applied to
these pins. See Section
Receive Alarm Interrupt 1. Flags host controller during alarm
conditions defined in Status Register 1. Active low, open drain output.
Receive Alarm Interrupt 2. Flags host controller during conditions
defined in Status Register 2. Active low, open drain output.
Transmit Tip. Analog line driver output; connects to a step-up
transformer (see Section
Transmit Signal Ground. 0V. Should be tied to local ground plane.
Transmit Analog Positive Supply. 5.0V. Should be tied to DVDD and
RVDD pins.
Transmit Ring. Analog line driver outputs; connects to a step-up
transformer (see Section
Transmit Channel Block. A user-programmable output that can be
forced high or low during any of the 32 E1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in applications
where not all E1 channels are used such as Fractional E1, 384kbps
service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating
individual channels in drop-and-insert applications. See Section
timing details.
Transmit Link Clock. 4kHz to 20kHz demand clock for the TLINK
input. Controlled by TCR2. See Section
Transmit Link Data. If enabled, this pin will be sampled on the falling
edge of TCLK to insert the Sa bits. See Section
Transmit Sync. A pulse at this pin will establish either frame or
multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q
can be programmed to output either a frame or multiframe pulse at this
pin. See Section
Digital Positive Supply. 5.0V. Should be tied to RVDD and TVDD
pins.
Transmit Clock. 2.048MHz primary clock.
Transmit Serial Data. Transmit NRZ serial data, sampled on the
falling edge of TCLK.
Transmit Channel Clock. 256kHz clock that pulses high during the
LSB of each channel. Useful for parallel to serial conversion of channel
data. See Section
7 of 60
WR
14
14
(R/
for timing details.
for timing details.
W
13
13
13
) pins. If BTS = 1, then these pins assume the
for crystal specifications.
for details).
for details).
FUNCTION
14
13
for timing details.
for details).
14
for timing details.
RD
(DS),
14
for