DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet - Page 6

• Manufacturer Part Number: DS2153QN-A7/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2153QN-A7/T&R

• Product: Framer
• Number Of Transceivers: 1
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.8 V
• Part # Aliases: 90-2153Q-NT7

2 PIN DESCRIPTION
41–44
1–4,
PIN
10
11
12
13
14
15
16
17
18
19
5
6
7
8
9
RLOS/LOTC
AD4–AD7,
AD0–AD3
WR
RCHCLK
RCHBLK
ALE(AS)
SYSCLK
RSYNC
RLCLK
RD
NAME
RLINK
ACLKI
RCLK
DVSS
RSER
CS
(R/
(DS)
W
)
TYPE
I/O
I/O
—
O
O
O
O
O
O
O
I
I
I
I
I
I
Address/Data Bus. An 8-bit multiplexed address/data bus.
Active-Low Read Input (Data Strobe)
Active-Low Chip Select. Must be low to read or write the port.
Address Latch Enable (Address Strobe). A positive going edge
serves to demultiplex the bus.
Active-Low Write Input (Read/Write)
Receive Link Data. Outputs the full receive data stream including the
Sa bits. See Section
Receive Link Clock. 4kHz to 20kHz demand clock for the RLINK
output. Controlled by RCR2. See Section
Digital Signal Ground. 0.0V. Should be tied to local ground plane.
Receive Clock. Recovered 2.048MHz clock.
Receive Channel Clock. 256kHz clock that pulses high during the
LSB of each channel. Useful for parallel to serial conversion of
channel data. See Section
Receive Serial Data. Received NRZ serial data, updated on rising
edges of RCLK or SYSCLK.
Receive Sync. An extracted pulse, one RCLK wide, is output at this
pin, which identifies either frame (RCR1.6 = 0) or multiframe
boundaries (RCR1.6 = 1). If the elastic store is enabled via the
RCR2.1, then this pin can be enabled to be an input via RCR1.5 at
which a frame boundary pulse is applied. See Section
details.
Receive Loss of Sync/Loss of Transmit Clock. A dual function
output. If TCR2.0 = 0, will toggle high when the synchronizer is
searching for the E1 frame and multiframe; if TCR2.0 = 1, will toggle
high if the TCLK pin has not toggled for 5µs.
System Clock. 1.544MHz or 2.048MHz clock. Only used when the
elastic store functions are enabled via either RCR2.1. Should be tied
low in applications that do not use the elastic store. If tied high for at
least 100µs, will force all output pins (including the parallel port) to
tri-state.
Receive Channel Block. A user-programmable output that can be
forced high or low during any of the 32 E1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in applications
where not all E1 channels are used such as Fractional E1, 384kbps
service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating
individual channels in drop-and-insert applications. See Section
timing details.
Alternate Clock Input. Upon a receive carrier loss, the clock applied
at this pin (normally 2.048MHz) will be routed to the RCLK pin. If no
clock is routed to this pin, then it should be tied to DVSS via a 1kΩ
resistor.
6 of 60
14
for timing details.
14
FUNCTION
for timing details.
14
for timing details.
14
for timing
14
for