DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet - Page 40

• Manufacturer Part Number: DS2153QN-A7/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2153QN-A7/T&R

• Product: Framer
• Number Of Transceivers: 1
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.8 V
• Part # Aliases: 90-2153Q-NT7

DS2153Q
13.1 Receive Clock and Data Recovery
The DS2153Q contains a digital clock recovery system. See
Figure 1-1
and
Figure 13-1
for more details.
The DS2153Q couples to the receive E1 twisted pair or coax via a 1:1 transformer. See
Table 13-3
for
transformer details. The DS2153Q automatically adjusts to the E1 signal being received at the RTIP and
RRING pins and can handle E1 twisted pair cables of 0.6mm (22 AWG) from 0 to 1.5km in length. The
crystal attached at the XTAL1 and XTAL2 pins is multiplied by 4 via an internal PLL and fed to the
clock recovery system. The clock recovery system uses both edges of the clock from the PLL circuit to
form a 32 times oversampler that is used to recover the clock and data. This oversampling technique
offers outstanding jitter tolerance (see
Figure
13-2).
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI waveform
presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a Receive
Carrier Loss (RCL) condition will occur and the RCLK can be sourced from either the ACLKI pin or
from the crystal attached to the XTAL1 and XTAL2 pins. The DS2153Q will sense the ACLKI pin to
determine if a clock is present. If no clock is applied to the ACLKI pin, then it should be tied to RVSS to
prevent the device from falsely sensing a clock. See
Table
13-1. If the jitter attenuator is either placed in
the transmit path or is disabled, the RCLK output can exhibit short high cycles of the clock. This is due to
the highly oversampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path
(as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty
cycle. See the receive AC timing characteristics in Section
16
for more details.
Table 13-1. Source of RCLK Upon RCL
RECEIVE SIDE JITTER
TRANSMIT SIDE JITTER
ACLKI PRESENT?
ATTENUATOR
ATTENUATOR
Yes
ACLKI via the jitter attenuator
ACLKI
No
Centered crystal
TCLK via the jitter attenuator
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