DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet - Page 42

• Manufacturer Part Number: DS2153QN-A7/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2153QN-A7/T&R

• Product: Framer
• Number Of Transceivers: 1
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.8 V
• Part # Aliases: 90-2153Q-NT7

13.3 Jitter Attenuator
The DS2153Q contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.
The characteristics of the attenuation are shown in
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order
for the jitter attenuator to operate properly, a crystal with the specifications listed in
connected to the XTAL1 and XTAL2 pins.
The jitter attenuator divides the clock provided by the 8.192MHz crystal at the XTAL1 and XTAL2 pins
to create an output clock that contains very little jitter. On-board circuitry will pull the crystal (by
switching in or out load capacitance) to keep it long-term averaged to the same frequency as the incoming
E1 signal. If the incoming jitter exceeds either 120UI
is 32 bits), then the DS2153Q will divide the attached crystal by either 3.5 or 4.5 instead of the normal 4
to keep the buffer from overflowing. When the device divides by either 3.5 or 4.5, it also sets the Jitter
Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR.5).
Table 13-4. Crystal Selection Guidelines
Parallel Resonant Frequency
Mode
Load Capacitance
Tolerance
Pullability
Effective Series Resistance
Crystal Cut
PARAMETER
8.192MHz
Fundamental
18pF to 20pF (18.5pF nominal)
±50ppm
C
+250ppm
C
30Ω maximum
AT
L
L
= 10pF, delta frequency = +175ppm to
= 45pF, delta frequency = -175ppm to -250ppm
42 of 60
SPECIFICATION
P-P
Figure
(buffer depth is 128 bits) or 28UI
13-4. The jitter attenuator can be placed in
Table 13-4
P-P
(buffer depth
must be