DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet - Page 32

• Manufacturer Part Number: DS2153QN-A7/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2153QN-A7/T&R

• Product: Framer
• Number Of Transceivers: 1
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.8 V
• Part # Aliases: 90-2153Q-NT7

9 TRANSMIT IDLE REGISTERS
There is a set of five registers in the DS2153Q that can be used to custom tailor the data that is to be
transmitted onto the E1 line, on a channel-by-channel basis. Each of the 32 E1 channels can be forced to
have a user-defined idle code inserted into them.
TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address = 26 to 29 Hex)
Note: If CCR3.5 = 1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies that channel data is to be
sourced from the RSER pin.
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex)
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represents a time slot in
the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). In the TIDR, the MSB is transmitted first. Via
the CCR3.5 bit, the user has the option to use the TIRs to determine on a channel-by-channel basis, if data
from the RSER pin should be substituted for data from the TSER pin. In this mode, if the corresponding
bit in the TIRs is set to 1, then data will be sourced from the RSER pin. If the corresponding bit in the
TIRs is set to 0, then data for that channel will sourced from the TSER pin. See the Transmit Data Flow
diagram in Section
(MSB)
CH16
CH24
CH32
CH8
(MSB)
TIDR7
SYMBOL
SYMBOL
CH32
CH1
TIDR7
TIDR0
CH15
CH23
CH31
CH7
TIDR6
14
for more details.
POSITION
CH14
CH22
CH30
CH6
TIR4.7
TIR1.0
TIDR5
POSITION NAME AND DESCRIPTION
TIDR.7
TIDR.0
CH13
CH21
CH29
CH5
NAME AND DESCRIPTION
Transmit Idle Registers.
0 = do not insert the Idle Code into this channel
1 = insert the Idle Code into this channel
TIDR4
MSB of the Idle Code
LSB of the Idle Code
CH12
CH20
CH28
CH4
32 of 60
TIDR3
CH11
CH19
CH27
CH3
TIDR2
CH10
CH18
CH26
CH2
TIDR1
CH17
CH25
(LSB)
CH9
CH1
TIR2 (27)
TIR3 (28)
TIR4 (29)
TIR1 (26)
TIDR0
(LSB)