DS2153QN-A7/T&R Maxim Integrated, DS2153QN-A7/T&R Datasheet - Page 39

• Manufacturer Part Number: DS2153QN-A7/T&R
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2153QN-A7/T&R

• Product: Framer
• Number Of Transceivers: 1
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.8 V
• Part # Aliases: 90-2153Q-NT7

13 LINE INTERFACE FUNCTIONS
The line interface function in the DS2153Q contains three sections: the receiver, which handles clock and
data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of
these three sections is controlled by the Line Interface Control Register (LICR), which is described
below.
LICR: LINE INTERFACE CONTROL REGISTER (Address = 18 Hex)
(MSB)
LB2
LB1
SYMBOL POSITION NAME AND DESCRIPTION
JABDS
EGL
TPD
DJA
LB2
LB1
LB0
JAS
LB0
LICR.7
LICR.6
LICR.5
LICR.4
LICR.3
LICR.2
LICR.1
LICR.0
EGL
Line Build-Out Select Bit 2. Sets the transmitter build
out; see the
Line Build-Out Select Bit 1. Sets the transmitter build
out; see the
Line Build-Out Select Bit 0. Sets the transmitter build
out; see the
Receive Equalizer Gain Limit.
0 = -12dB
1 = -30dB
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power Down.
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP
and TRING pins
39 of 60
JAS
Table
Table
Table
JABDS
13-2.
13-2.
13-2.
DJA
(LSB)
TPD
LICR