ADE7759ARSRL Analog Devices Inc, ADE7759ARSRL Datasheet - Page 11

• Manufacturer Part Number: ADE7759ARSRL
• Description: IC ENERGY METERING 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7759ARSRL

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7759EBZ - BOARD EVALUATION FOR ADE7759

Test Circuits
ANALOG INPUTS
The ADE7759 has two fully differential voltage input channels.
The maximum differential input voltage for input pairs V1P/V1N
and V2P/V2N are ± 0.5 V. In addition, the maximum signal
level on analog inputs for V1P/V1N and V2P/V2N are ± 0.5 V
with respect to AGND.
Each analog input channel has a PGA (Programmable Gain
Amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the gain register—see
Figure 5. Bits 0 to 2 select the gain for the PGA in Channel 1 and
the gain selection for the PGA in Channel 2 is made via Bits 5
to 7. Figure 4 shows how a gain selection for Channel 1
is made using the gain register.
REV. A
Test Circuit 1. Performance Curve (Integrator OFF)
110V
CT TURN RATIO = 1800:1
CHANNEL 2 GAIN = 1
I
GAIN (CH1)
CH1OS[7:0]
BIT 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION
BIT 6: NOT USED
BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT ON)
1
4
10 F
600k
RB
1k
10 F
1k
V1N
10
2.5
V1P
V
RB
IN
1k
100nF
33nF
1k
33nF
33nF
33nF
Figure 4. PGA in Channel 1
100nF
GAIN[7:0]
AV
V1P
V1N
V2N
V2P
REF
DD
V
ADE7759
DD
IN/OUT
AGND DGND
K
DV
U1
DD
V
IN
CLKOUT
RESET
CLKIN
DOUT
SCLK
SAG
IRQ
DIN
CS
GAIN (K)
SELECTION
ZX
CF
100nF
+
OFFSET ADJUST
( 50mV)
NOT CONNECTED
TO SPI BUS
(USED ONLY FOR
CALIBRATION)
Y1
3.58MHz
22pF
PS2501-1
10 F
U3
22pF
TO
FREQUENCY
COUNTER
–11–
In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The ADC analog input range
selection is also made using the gain register—see Figure 5. As
mentioned previously the maximum differential input voltage is
0.5 V. However, by using Bits 3 and 4 in the gain register, the
maximum ADC input voltage can be set to 0.5 V, 0.25 V, or
0.125 V. This is achieved by adjusting the ADC reference—see
Reference Circuit section. Table I summarizes the maximum
differential input signal level on Channel 1 for the various ADC
range and gain selections.
Max Signal
Channel 1
0.5 V
0.25 V
0.125 V
0.0625 V
0.0313 V
0.0156 V
0.00781 V
PGA 2 GAIN SELECT
000 =
001 =
010 =
011 =
100 =
I
Test Circuit 2. Performance Curve (Integrator ON)
110V
Table I. Maximum Input Signal Levels for Channel 1
di/dt CURRENT
SENSOR
CHANNEL 1 GAIN = 4
CHANNEL 2 GAIN = 1
1
2
4
8
16
10 F
100
600k
33nF
33nF
100
CHANNEL 1 AND CHANNEL 2 PGA CONTROL
1k
*REGISTER CONTENTS
10 F
1k
SHOW POWER-ON DEFAULTS
7
0
Figure 5. Analog Gain Register
100nF
1k
1k
33nF
33nF
6
0
33nF
33nF
0.5 V
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
5
0
GAIN REGISTER*
100nF
4
0
AV
V1P
V1N
V2N
V2P
REF
ADC Input Range Selection
DD
V
ADE7759
DD
IN/OUT
AGND DGND
3
0
DV
U1
DD
2
0
CLKOUT
RESET
CLKIN
DOUT
SCLK
0.25 V
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
SAG
IRQ
1
0
DIN
CS
ZX
CF
100nF
CHANNEL 1 FULL-SCALE SELECT
00 = 0.5V
01 = 0.25V
10 = 0.125V
0
0
PGA 1 GAIN SELECT
000 =
001 =
010 =
011 =
100 =
ADDR:
0AH
NOT CONNECTED
ADE7759
TO SPI BUS
(USED ONLY FOR
CALIBRATION)
Y1
3.58MHz
22pF
PS2501-1
10 F
U3
1
2
4
8
16
0.125 V
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
22pF
TO
FREQUENCY
COUNTER