ADE7759ARSRL Analog Devices Inc, ADE7759ARSRL Datasheet - Page 18

• Manufacturer Part Number: ADE7759ARSRL
• Description: IC ENERGY METERING 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7759ARSRL

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7759EBZ - BOARD EVALUATION FOR ADE7759

ADE7759
0.5V, 0.25V,
0.125V, 62.5mV,
31.3mV, 15.6mV,
Channel 1 ADC Gain Adjust
The ADC gain in Channel 1 can be adjusted by using the multi-
plier and active power gain register (APGAIN[11:0]). The gain of
the ADC is adjusted by writing a twos complement 12-bit word
to the active power gain register. Below is the expression that
shows how the gain adjustment is related to the contents of the
active power gain register.
For example, when 7FFh is written to the active power gain
register, the ADC output is scaled up by 50%. 7FFh = 2047
decimal, 2047/2
(signed twos complement) and ADC output is scaled by –50%.
These two examples are illustrated in Figure 23.
Channel 1 Sampling
The waveform samples may also be routed to the waveform
register (MODE[14:13] = 1, 0) to be read by the system master
(MCU). In waveform sampling mode, the WSMP bit (Bit 3) in
the interrupt enable register must also be set to Logic 1. The
active power and energy calculation will remain uninterrupted
during waveform sampling.
When in waveform sample mode, one of four output sample
rates may be chosen by using Bits 11 and 12 of the mode regis-
ter DTRT(1, 0). The output sample rate may be 27.9 kSPS,
14 kSPS, 7 kSPS, or 3.5 kSPS—see Mode Register section. The
interrupt request output IRQ signals a new sample availability
by going active low. The timing is shown in Figure 24. The 20-bit
0V
V1
*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA VARIES DEPENDING
ON THE SIGNAL FREQUENCY BECAUSE OF –20dB/DECADE FREQUENCY RESPONSE.
ANALOG
INPUT
RANGE
Code
12
V1
V1P
= 0.5. Similarly, 801h = 2047 decimal
V1N
=
PGA1



{GAIN[2:0]}
ADC
1,
8,
D7AE1h
C0000h
40000h
2851Fh
00000h
2,
16
×
4,
2.42V, 1.21V, 0.6V



1
REFERENCE
ADC 1
+
ADC OUTPUT
WORD RANGE
Figure 23. ADC and Signal Processing in Channel 1
APGAIN
2
12
801HEX–7FFHEX
APGAIN[11:0]
MULTIPLIER
+FS
+63% FS
{GAIN[4:3]}
– 63% FS
– FS






DIGITAL LPF
3C7AEh
EBD71h
D7AE1h
C3852h
2851Fh
1428Fh
00000h
Sinc
3
–18–
000h 7FFh
CHANNEL 1 (ACTIVE POWER)
DATA RANGE
APGAIN[11:0]
wave form samples are transferred from the ADE7759 one byte
(eight bits) at a time, with the most significant byte shifted out
first. The 20-bit dataword is right justified and sign extended to
24 bits (three bytes)—see Serial Interface section.
CHANNEL 1 AND CHANNEL 2 WAVEFORM SAMPLING
MODE
In Channel 1 and Channel 2 waveform sampling mode
(MODE[14:13] = 01), the output is a 40-bit waveform sample
data that contains the waveform samples from both Channel 1
and Channel 2 ADCs. Figure 25 shows the format of the 40-bit
waveform output.
Figure 25. 40-Bit Combined Channel 1 and Channel 2
Waveform Sample Data Format
DOUT
SCLK
HPF
IRQ
DIN
BIT 39
CH2[19:16] CH1[19:16]
801h
Figure 24. Waveform Sampling Channel 1
INTEGRATOR*
16 s
1 BYTE
DIGITAL
SAMPLING RATE (27.9kSPS, 14kSPS, 7kSPS, OR 3.5kSPS)
+94.5% FS
+63% FS
+31.5% FS
– 31.5% FS
– 63% FS
– 94.5% FS
READ FROM WAVEFORM
∫
0
0 0 01 HEX
50Hz
19CE0h
0CE70h
D94B0h
26B50h
E6320h
00000h
F3190h
D18D2h
2E72Eh
E108Ch
1EF74h
F0846h
CH1[15:0]
00000h
F7BAh
60Hz
TO WAVEFORM
SAMPLE REGISTER
TO MULTIPLIER
2 BYTES
000h 7FFh 801h
CHANNEL 1 (ACTIVE POWER)
DATA RANGE AFTER
INTEGRATOR (60Hz)
SIGN
APGAIN[11:0]
000h 7FFh
CHANNEL 1 (ACTIVE POWER)
DATA RANGE AFTER
INTEGRATOR (50Hz)
APGAIN[11:0]
CHANNEL 1 DATA
– 20 BITS
801h
CH2[15:0]
2 BYTES
+94.5%
+63%
+31.5%
– 31.5%
– 63%
– 94.5%
+94.5% FS
+63% FS
+31.5% FS
– 31.5% FS
– 63% FS
– 94.5% FS
FS
FS
FS
FS
FS
FS
BIT 0
REV. A