ADE7759ARSRL Analog Devices Inc, ADE7759ARSRL Datasheet - Page 33

• Manufacturer Part Number: ADE7759ARSRL
• Description: IC ENERGY METERING 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7759ARSRL

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7759EBZ - BOARD EVALUATION FOR ADE7759

CH1OS Register (08H)
The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch on/off the digital integrator in Chan-
nel 1, and Bits 0 to 5 indicate the amount of the offset correction in Channel 1. Table VIII summarizes the function of this register.
Bit Location
0 to 5
6
7
REV. A
(END OF A HARDWARE OR SOFTWARE RESET)
(ACTIVE ENERGY REGISTER OVERFLOW)
Bit Mnemonic
OFFSET
Not Used
INTEGRATOR
(ACTIVE ENERGY REGISTER OVERFLOW)
(TEMPERATURE REGISTER READY)
(TEMPERATURE REGISTER READY)
(ZERO CROSSING DETECTED)
DIGITAL INTEGRATOR SELECTION
(ZERO CROSSING DETECTED)
Description
The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1
ADC. The 6-bit offset correction is sign and magnitude coded. Bits 0 to 4 indicate the magnitude
of the offset correction. Bit 5 shows the sign of the offset correction. A 0 in Bit 5 means the offset
correction is positive and a 1 indicates the offset correction is negative.
This bit is unused.
This bit is used to activate the digital integrator on Channel 1. The digital integrator is switched
on by setting this bit. This bit is set to be 1 on default.
NOT USED
0 = DISABLE
1 = ENABLE
AEOF
TEMP
NOTE: REGISTER CONTENTS SHOW POWER ON DEFAULTS
RESET
ZX
*REGISTER CONTENTS SHOW POWER-ON DEFAULT
Figure 49. Interrupt Status Register
Figure 50. Interrupt Enable Register
NOTE: REGISTER CONTENTS SHOW POWER ON DEFAULTS
AEOF
TEMP
ZX
Figure 51. CH1OS Register
Table VIII. CH1OS Register
7
0
6
0
7
0
7
1
5
6
0
1
6
0
CH1OS REGISTER*
5
4
0
0
5
0
–33–
0
4
3
0
4
0
2
0
3
0
3
0
1
0
2
0
2
0
0
0
1
0
1
0
ADDR: 10H
0
0
0
0
ADDR: 04H/RESET: 05H
AEHF
(ACTIVE ENERGY REGISTER HALF FULL)
SAG
(LINE VOLTAGE SAG DETECT)
CYCEND
(END OF LINE CYCLE ENERGY ACCUMULATION)
WSMP
(WAVEFORM SAMPLING)
ADDR: 08H
AEHF
(ACTIVE ENERGY REGISTER HALF FULL)
SAG
(LINE VOLTAGE SAG DETECT)
CYCEND
(LINE CYCLE ENERGY ACCUMULATION END)
WSMP
(WAVEFORM SAMPLING)
SIGN AND MAGNITUDE CODED
OFFSET CORRECTION BITS
NOT USED
ADE7759