ADE7759ARSRL Analog Devices Inc, ADE7759ARSRL Datasheet
ADE7759ARSRL
Specifications of ADE7759ARSRL
Related parts for ADE7759ARSRL
ADE7759ARSRL Summary of contents
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FEATURES High Accuracy, Supports IEC 687/1036 On-Chip Digital Integrator Allows Direct Interface with Current Sensors with di/dt Output Such as Rogowski Coil Less Than 0.1% Error over a Dynamic Range of 1000 to 1 On-Chip User-Programmable Threshold for Line ...
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ADE7759 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SPECIFICATIONS T MIN Parameter ENERGY MEASUREMENT ACCURACY Measurement Bandwidth 1 Measurement Error on Channel 1 Channel 1 Range = 0.5 V Full-Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Channel ...
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ADE7759–SPECIFICATIONS Parameter REFERENCE INPUT REF Input Voltage Range IN/OUT Input Capacitance ON-CHIP REFERENCE Reference Error Current Source Output Impedance Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS RESET, DIN, SCLK, CLKIN, and CS Input High Voltage, V INH Input Low ...
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TIMING CHARACTERISTICS Parameter A, B Versions Unit Write Timing (min 150 ns (min 150 ns (min (min (min (min ...
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... ADE7759 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model ADE7759ARS ADE7759ARSRL EVAL-ADE7759EB *RS = Shrink Small Outline Package in tubes; RSRL = Shrink Small + 0 Outline Package in reel. ...
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Pin No. Mnemonic Description RESET 1 Reset Pin for the ADE7759. A logic low on this pin will hold the ADCs and digital circuitry (including the serial interface reset condition Digital Power Supply. This pin provides ...
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ADE7759 Pin No. Mnemonic Description 12 ZX Voltage Waveform (Channel 2) Zero Crossing Output. This output toggles logic high and low at the zero crossing of the differential signal on Channel 2—see Zero Crossing Detection section. SAG 13 This open-drain ...
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0.3 + 0.2 0.1 0.0 –0.1 + –0.2 FULL SCALE = 0.5V –0.3 GAIN = 1 INTEGRATOR OFF –0.4 INTERNAL REFERENCE –0.5 0.01 0.1 1 ...
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ADE7759 0.5 0.4 0.3 – 0.2 0.1 0.0 –0.1 –0.2 FULL SCALE = 0.5V –0.3 GAIN = 4 INTEGRATOR OFF –0.4 EXTERNAL REFERENCE –0.5 0.01 0.1 1 CURRENT – A TPC 7. Error ...
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Test Circuits 100nF 100nF RESET DIN 1k V1P 33nF DOUT RB 1k SCLK V1N U1 33nF CS ADE7759 CLKOUT V2N 1k 33nF CLKIN 600k V2P IRQ 110V 33nF 1k SAG ZX ...
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ADE7759 It is also possible to adjust offset errors on Channel 1 and Channel 2 by writing to the offset correction registers (CH1OS and CH2OS, respectively). These registers allow channel offsets in the range ± ± 50 ...
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FREQUENCY – Hz Figure 10. Gain Response of the Digital Integrator –88.0 –88.5 –89.0 –89.5 –90.0 –90.5 –91.0 –91.5 –92 FREQUENCY – ...
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ADE7759 The ZX signal will go logic high on a positive going zero crossing and logic low on a negative going zero crossing on Channel 2. The zero crossing signal ZX is generated from the output of LPF1. LPF1 has ...
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INTERRUPTS ADE7759 interrupts are managed through the interrupt status register (STATUS[7:0]) and the interrupt enable register (IRQEN[7:0]). When an interrupt event occurs in the ADE7759, the corresponding flag in the status register is set to a Logic 1—see Interrupt Status ...
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ADE7759 TEMPERATURE MEASUREMENT ADE7759 also includes an on-chip temperature sensor. A temperature measurement can be made by setting Bit 5 in the mode register. When Bit 5 is set logic high in the mode register, the ADE7759 will initiate a ...
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ALIASING EFFECTS IMAGE FREQUENCIES 0 2 447 FREQUENCY – kHz Figure 21. ADC and Signal Processing in Channel 1 For a di/dt sensor such as a Rogowski coil, however, the sensor has 20 dB per decade gain. This will neutralize ...
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ADE7759 2.42V, 1.21V, 0. REFERENCE 8, 16 {GAIN[2:0]} V1P ADC 1 PGA1 V1 V1N V1 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV, 15.6mV, 40000h 0V 2851Fh 00000h ANALOG INPUT RANGE D7AE1h C0000h ADC OUTPUT WORD RANGE *WHEN DIGITAL INTEGRATOR ...
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CHANNEL 2 ADC Channel 2 Sampling In Channel 2 waveform sampling mode (MODE[14:13 and WSMP = 1), the ADC output code scaling for Channel 2 is the same as Channel 1, i.e., the output swings between D7AE1h ...
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ADE7759 V1P HPF PGA1 ADC 1 V1 V1N V2P 1 DELAY BLOCK PGA2 ADC 2 V2 1.12 s/LSB V2N PHCAL [7:0] 0.1 –110 s TO +103 s V1 60Hz Figure 28. Phase ...
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INSTANTANEOUS p( – POWER SIGNAL 1999Ah VI CCCDh 00000h CURRENT i( sin( t) VOLTAGE v( sin( t) Figure 32. Active Power Calculation 0 –4 –8 –12 –16 –20 –24 ...
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ADE7759 CURRENT CHANNEL VOLTAGE CHANNEL AENERGY [39:0] 7F,FFFF,FFFFh 3F,FFFF,FFFFh 00,0000,0000h 23s 5.8s 11.5s 40,0000,0000 80,0000,0000h Figure 37. Energy Register Rollover Time for Full-Scale Power (Minimum and Maximum Power Gain) Note that the energy register contents will roll over to full-scale ...
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This output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. Figure 38 illustrates the energy-to-frequency con- version in the ADE7759. The energy-to-frequency conversion is accomplished by accu- mulating the active power signal in ...
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ADE7759 E(t) Vlt VI – 4 ƒ 2ƒ /8.9Hz Figure 39. Output Frequency Ripple LINE CYCLE ENERGY ACCUMULATION MODE In line cycle energy accumulation mode, the energy accumula- tion of the ADE7759 can be synchronized to ...
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For 255 half cycles this would give a total integration time of 2.125 seconds. This would mean that the energy register was updated 2.125/1.1175 µs (4/CLKIN) times. The average output value of LPF2 is given as: Contents of LENERGY [ ...
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ADE7759 Table III. Frequency Dependencies of the ADE7759 Parameters Parameter Nyquist frequency for CH 1 and 2 ADCs CLKIN/8 PHCAL resolution (seconds per LSB) Active Energy register update rate (Hz) Waveform sampling rate (Number of samples per second) WAVSEL 1, ...
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As explained earlier, the data write is initiated by a write to the communications register followed by the data. During a data write operation to the ADE7759, data is transferred to all on-chip registers one byte at a time. After ...
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ADE7759 CHECKSUM REGISTER The ADE7759 has a checksum register (CHKSUM[5:0]) to ensure that the data bits received in the last serial read operation are not corrupted. The 6-bit checksum register is reset before the first bit (MSB of the register ...
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Address Name R/W No. of Bits 0Bh APGAIN R/W 12 0Ch PHCAL R/W 8 0Dh APOS R/W 16 0Eh ZXTOUT R/W 12 0Fh SAGCYC R/W 8 10h IRQEN R/W 8 11h SAGLVL R/W 8 12h TEMP R 8 13h LINECYC ...
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ADE7759 REGISTER DESCRIPTIONS All ADE7759 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register and then transferring the register data. A full description of the serial interface protocol is given in ...
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Mode Register (06H) The ADE7759 functionality is configured by writing to the mode register—see Figure 45. Table VI summarizes the functionality of each bit in the mode register. Bit Bit Location Mnemonic Description 0 DISHPF The HFP (high-pass filter) in ...
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ADE7759 TEST1 (TEST MODE SELECTION SHOULD BE SET TO 0) WAVSEL (WAVEFORM SELECTION FOR SAMPLE MODE LPF2 01 = CH1 + CH2 (40-BIT WAVEFORM SAMPLES CH1 11 = CH2 DTRT (WAVEFORM SAMPLES OUTPUT DATA RATE) 00 ...
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ENERGY REGISTER OVERFLOW) (END OF A HARDWARE OR SOFTWARE RESET) (TEMPERATURE REGISTER READY) (ZERO CROSSING DETECTED) (ACTIVE ENERGY REGISTER OVERFLOW) (TEMPERATURE REGISTER READY) (ZERO CROSSING DETECTED) CH1OS Register (08H) The CH1OS register is an 8-bit, read/write enabled register. The ...
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ADE7759 0.05 MIN COPLANARITY OUTLINE DIMENSIONS 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters 7.50 7.20 6. 8.20 5.60 7.80 5.30 7.40 5. 1.85 1.75 2.00 MAX 1.65 0.25 0.09 8 0.65 0.38 ...
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Revision History Location 12/02—Data Sheet changed from REV REV. A. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . ...
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