ADE7759ARSRL Analog Devices Inc, ADE7759ARSRL Datasheet - Page 14

• Manufacturer Part Number: ADE7759ARSRL
• Description: IC ENERGY METERING 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7759ARSRL

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7759EBZ - BOARD EVALUATION FOR ADE7759

ADE7759
The ZX signal will go logic high on a positive going zero crossing
and logic low on a negative going zero crossing on Channel 2.
The zero crossing signal ZX is generated from the output of
LPF1. LPF1 has a single pole at 156 Hz (CLKIN = 3.579545 MHz).
As a result, there will be a phase lag between the analog input
signal V2 and the output of LPF1. The phase response of this
filter is shown in the Channel 2 Sampling section. The phase
lag response of LPF1 results in a time delay of approximately
0.97 ms (@ 60 Hz) between the zero crossing on the analog
inputs of Channel 2 and the rising or falling edge of ZX.
The zero crossing detection also has an associated timeout reg-
ister, ZXTOUT. This unsigned, 12-bit register is decremented
1 LSB every 128/CLKIN seconds. The register is reset to its
user-programmed full-scale value every time a zero crossing on
Channel 2 is detected. The default power-on value in this regis-
ter is FFFh. If the register decrements to zero before a zero
crossing is detected and the DISSAG bit in the mode register is
logic zero, the SAG pin will go active low. The absence of a zero
crossing is also indicated on the IRQ output if the SAG Enable
bit in the interrupt enable register is set to Logic 1. Irrespective
of the enable bit setting, the SAG flag in the interrupt status
register is always set when the ZXTOUT register is decremented
to zero—see Interrupts section. The zero cross timeout register
can be written/read by the user and has an address of 0Eh—see
Serial Interface section. The resolution of the register is 128/CLKIN
seconds per LSB. Thus the maximum delay for an interrupt
is 0.15 second (128/CLKIN × 2
LINE VOLTAGE SAG DETECTION
In addition to the detection of the loss of the line voltage signal
(zero crossing), the ADE7759 can also be programmed to detect
when the absolute value of the line voltage drops below a certain
peak value, for a number of half cycles. This condition is illus-
trated in Figure 15.
Figure 15 shows the line voltage fall below a threshold that is set
in the sag level register (SAGLVL[7:0]) for nine half cycles.
Since the sag cycle register (SAGCYC[7:0]) contains 06h, the
SAG pin will go active low at the end of the sixth half cycle for
which the line voltage falls below the threshold, if the DISSAG
bit in the mode register is Logic 0. As is the case when zero
crossings are no longer detected, the sag event is also recorded
by setting the SAG flag in the interrupt status register. If the
SAG enable bit is set to Logic 1, the IRQ logic output will go
active low—see Interrupts section.
FULL SCALE
SAGLVL [7:0]
SAG
SAGCYC [7:0] = 06H
Figure 15. Sag Detection
6 HALF CYCLES
CHANNEL 2
12
).
SAG RESET HIGH
WHEN CHANNEL 2
EXCEEDS SAGLVL [7:0]
–14–
The SAG pin will go logic high again when the absolute value of
the signal on Channel 2 exceeds the sag level set in the Sag
Level register. This is shown in Figure 15 when the SAG pin
goes high during the tenth half cycle from the time when the
signal on Channel 2 first dropped below the threshold level.
Sag Level Set
The contents of the sag level register (1 byte) are compared to
the absolute value of the most significant byte output from
LPF1, after it is shifted left by one bit. For example, the nomi-
nal maximum code from LPF1 with a full-scale signal on
Channel 2 is 257F6h or (0010, 0101, 0111, 1111, 0110b)—see
Channel 2 Sampling section. Shifting one bit left will give 0100,
1010, 1111, 1110, 1100b, or 4AFECh. Therefore, writing 4Ah
to the sag level register will put the sag detection level at full
scale. Writing 00h will put the sag detection level at zero. The
sag level register is compared to the most significant byte of a
waveform sample after the shift left, and detection is made when
the contents of the sag level register are greater.
POWER SUPPLY MONITOR
The ADE7759 also contains an on-chip power supply monitor.
The analog supply (AV
ADE7759. If the supply is less than 4 V ± 5%, the ADE7759
will go into an inactive state, i.e., no energy will be accumulated
when the supply voltage is below 4 V. This is useful to ensure
correct device operation at power-up and during power-down.
The power supply monitor has built-in hysteresis and filtering.
This gives a high degree of immunity to false triggering due to
noisy supplies.
As seen in Figure 16, the trigger level is nominally set at 4 V.
The tolerance on this trigger level is about ± 5%. The SAG pin
can also be used as a power supply monitor input to the MCU.
The SAG pin will go logic low when the ADE7759 is reset. The
power supply and decoupling for the part should be such that
the ripple at AV
normal operation.
Bit 6 of the interrupt status register (STATUS[7:0]) will be set
to logic high upon power-up or every time the analog supply
(AV
and recovers. However, no interrupt can be generated because
the corresponding bit (Bit 6) in the interrupt enable register
(IRQEN[7:0]) is not active—see Interrupts section.
POWER-ON
ADE7759
RESET
DD
AV
SAG
DD
5V
4V
0V
) dips below the power supply monitor threshold (4 V ± 5%)
Figure 16. On-Chip Power Supply Monitor
INACTIVE
DD
does not exceed 5 V ± 5% as specified for
DD
) is continuously monitored by the
ACTIVE
TIME
INACTIVE
REV. A