ADE7759ARSRL Analog Devices Inc, ADE7759ARSRL Datasheet - Page 23

• Manufacturer Part Number: ADE7759ARSRL
• Description: IC ENERGY METERING 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7759ARSRL

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7759EBZ - BOARD EVALUATION FOR ADE7759

load conditions. This output frequency can provide a simple,
single-wire, optically isolated interface to external calibration
equipment. Figure 38 illustrates the energy-to-frequency con-
version in the ADE7759.
The energy-to-frequency conversion is accomplished by accu-
mulating the active power signal in a 24-bit register. An output
pulse is generated when there is a zero to one transition on the
MSB (most significant bit) of the register. Under steady load con-
ditions the output frequency is proportional to the active power.
The output frequency at CF, with full-scale ac signals on
Channel 1 and Channel 2 and CFDEN = 000h, CFNUM = 000h,
and APGAIN = 000h, is approximately 5.593 kHz. This can be
calculated as follows:
With the active power gain register set to 000h, the average
value of the instantaneous power signal (output of LPF2) is
CCCDh or 52,429 decimal. An output frequency is generated
on CF when the MSB in the energy-to-frequency register (24 bits)
toggles, i.e., when the register accumulates 2
register is updated 2
the update rate is 4/CLKIN or 1.1175 µs, the time between
MSB toggles (CF pulses) is given as:
Equation 8 gives an expression for the output frequency at the
Energy-to-Frequency (ETF) output with the contents of CFDEN
and CFNUM registers are both zero.
This output frequency is easily scaled by a pair of calibration
frequency divider registers (CFDEN[11:0] and CFNUM[11:0]).
These frequency scaling registers are 12-bit registers that can
scale the output frequency by 1 to 2
given by the expression below:
For example, if the CF output frequency is 5.59286 kHz while
the contents of CFNUM and CFDEN are zero, the CF output
frequency can be set to 25 Hz by writing 8 BDh (2237 in deci-
mal) to the CFDEN register and 00Ah (10 in decimal) to the
CFNUM register. Note that the CFNUM and CFDEN regis-
ters are meant only to scale down the frequency from the ETF
REV. A
CF Hz
ETF Output Hz
(
159 999 1 1175
)
.
=
ETF Output Hz
·
(
.
23
) =
/CCCDh times (or 159.999 times). Since
11
11
ms
Average LPF Output CLKIN
(
=
1 78799 10
CFNUM [11:0]
CFDEN [11:0]
20
)
.
×
CFNUM
CFDEN
ACTIVE POWER
LPF2
SIGNAL – P
12
·
. The output frequency is
2
2
25
–
Figure 38. Energy-to-Frequency Conversion
[ : ]
+
4
[ : ]
11 0
11 0
s
23
(
0
0
5592 86
. This means the
+
×
15
+
+
SIGN 2
1
.
1
23
23
MSB
TRANSITION
Hz
ENERGY-TO-FREQUENCY
6
)
(9)
(8)
2
5
WAVEFORM [23:0]
2
4
–23–
2
3
output. Therefore, the content of CFDEN should always be set
no less than that of the CFNUM register, i.e., the maximum
output frequency from CF pin will never exceed that of the ETF
output. The power-up default value for CFDEN is 3Fh and
CFNUM is 0h.
The output frequency will have a slight ripple at a frequency
equal to twice the line frequency. This is due to imperfect filter-
ing of the instantaneous power signal to generate the active
power signal—see Active Power Calculation section. Equation 3
gives an expression for the instantaneous power signal. This is
filtered by LPF2, which has a magnitude response given by
Equation 10:
The active power signal (output of LPF2) can be rewritten as:
where f
From Equation 6:
From Equation 12 it can be seen that there is a small ripple in
the energy calculation due to a sin(2ωt) component. This is
shown in Figure 39. The active energy calculation is shown by
the dashed straight line and is equal to V × I × t. The sinusoidal
ripple in the active energy calculation is also shown. Since the
average value of a sinusoid is zero, this ripple will not contribute
to the energy calculation over time. However, the ripple can be
observed in the frequency output, especially at higher output
frequencies. The ripple will get larger as a percentage of the
frequency at larger loads and higher output frequencies. The rea-
son is that at higher output frequencies the integration or averaging
time in the energy-to-frequency conversion process is shorter. As
a consequence, some of the sinusoidal ripple is observable in the
frequency output. Choosing a lower output frequency at CF for
calibration can significantly reduce the ripple. Also, averaging the
output frequency by using a longer gate time for the counter will
achieve the same results.
2
2
E t
H f
p t
( )
APOS [15:0]
( )
2
( )
1
=
l
=
2
is the line frequency (e.g., 60 Hz).
0
VI
VIt
=
2
1
–1
−
+
−



2
0
0



 
1 2
f
–2
4
/ .
+
1
8 9
π
2
–3
f
l
f
(
l
VI
1 2
+
+
Hz
2
/ .
–4
+
8 9
ACTIVE POWER OFFSET
2
VI
–5
f
CF
Hz
l
CALIBRATION
/ .
2
8 9
–6



cos
2
–7
Hz
(
2
4π
)
–8



 
0
f t
sin
l
)
(
4
π
ADE7759
f t
l
)
(10)
(11)
(12)