ADE7759ARSRL Analog Devices Inc, ADE7759ARSRL Datasheet - Page 24

• Manufacturer Part Number: ADE7759ARSRL
• Description: IC ENERGY METERING 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7759ARSRL

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7759EBZ - BOARD EVALUATION FOR ADE7759

ADE7759
LINE CYCLE ENERGY ACCUMULATION MODE
In line cycle energy accumulation mode, the energy accumula-
tion of the ADE7759 can be synchronized to the Channel 2 zero
crossing so that active energy can be accumulated over an inte-
gral number of half line cycles. The advantage of summing the
active energy over an integer number of half-line cycles is that
the sinusoidal component in the active energy is reduced to zero.
This eliminates any ripple in the energy calculation. Energy is
calculated more accurately and in a shorter time because the
integration period can be shortened. By using the line cycle
energy accumulation mode, the energy calibration can be greatly
simplified and the time required to calibrate the meter can be sig-
nificantly reduced. The ADE7759 is placed in line cycle energy
accumulation mode by setting Bit 7 (CYCMODE) in the mode
register. In line cycle energy accumulation mode the ADE7759
accumulates the active power signal in the LENERGY register
(Address 14h) for an integral number of half cycles, as shown in
Figure 40. The number of half-line cycles is specified in the
LINECYC register (Address 14h). The ADE7759 can accumu-
late active power for up to 16,383 half cycles. Because the active
power is integrated on an integral number of half-line cycles, at
the end of a line cycle energy accumulation cycle, the CYCEND
flag in the interrupt status register is set (Bit 2). If the CYCEND
enable bit in the interrupt enable register is enabled, the IRQ
output will also go active low. Thus the IRQ line can also be
used to signal the completion of the line cycle energy accumula-
tion. Another calibration cycle will start as long as the CYCMODE
bit in the mode register is set. Note that the result of the first
calibration is invalid and should be ignored. The result of all
subsequent line cycle accumulation is correct.
Figure 39. Output Frequency Ripple
E(t)
–
4 ƒ
Figure 40. Energy Calculation in Line Cycle Energy Accumulation Mode
l
(1 + 2ƒ
MULTIPLIER
CHANNEL 2
Vlt
15
SIGN 2
VI
CCCDh
FROM
l
ADC
/8.9Hz)
00h
6
2
5
2
LPF2
LPF1
sin(4 ƒ
4
ACTIVE POWER
2
3
SIGNAL – P
l
t)
2
2
+
APOS [15:0]
2
1
+
2
0
23
39
2
–1
ZERO CROSS
–24–
2
–2
DETECT
2
–3
From Equations 5 and 11:
where n is an integer and T is the line cycle period.
Since the sinusoidal component is integrated over an integer
number of line cycles, its value is always zero. Therefore:
Note that in this mode, the 14-bit LINECYC register can hold a
maximum value of 16,383. In other words, the line cycle
energy accumulation mode can be used to accumulate active
energy for a maximum duration over 16,383 half-line cycles. At
60 Hz line frequency, it translates to a total duration of 16,383/
120 Hz = 136.5 seconds. The 40-bit signed LENERGY register
can overflow if large signals are present at the inputs. The
LENERGY register can only hold up to 11.53 seconds of active
energy when both its input channels are at ac full-scale—see
Integration Time Under Steady Load section. Large LINECYC
content is meant to be used only when the input signal is low
and extensive averaging is required to reduce the noise.
CALIBRATING THE ENERGY METER
Calculating the Average Active Power
When calibrating the ADE7759, the first step is to calibrate the
frequency on CF to some required meter constant, e.g.,
3200 imp/kWh.
To determine the output frequency on CF, the average value of
the active power signal (output of LPF2) must first be deter-
mined. One convenient way to do this is to use the line cycle
energy accumulation mode. When the CYCMODE (Bit 7) bit
in the mode register is set to a Logic 1, energy is accumulated
over an integer number of half-line cycles as described in the
last section. Since the line frequency is fixed at, say, 60 Hz, and
the number of half cycles of integration is specified, the total
integration time is given as:
E t
E t
E t
WAVEFORM [23:0]
LENERGY [39:0]
2
( ) = ∫
( ) =
( )
–4
2
= ∫
–5
VInT
nT
nT
0
0
2
VIdt
VIdt
–6
LINECYC [13:0]
CALIBRATION
2
CONTROL
–7
+
2 60
–
2
0
×



 
–8
4
0
1
Hz
f
l
0
0
(
1 2
×
+
number of half cycles
VI
f
l
/ .
8 9
+
+
Hz
)



 
nT
0
∫
cos
(
2
wt dt
)
REV. A
(13)
(14)
(15)