C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 102

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F52x/F52xA/F53x/F53xA
SFR Definition 10.3. EIE1: Extended Interrupt Enable 1
102
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
EMAT
R/W
Bit7
EMAT: Enable Port Match Interrupt.
This bit sets the masking of the Port Match interrupt.
0: Disable the Port Match interrupt.
1: Enable the Port Match interrupt.
EREG0: Enable Voltage Regulator Interrupt.
This bit sets the masking of the Voltage Regulator Dropout interrupt.
0: Disable the Voltage Regulator Dropout interrupt.
1: Enable the Voltage Regulator Dropout interrupt.
ELIN: Enable LIN Interrupt.
This bit sets the masking of the LIN interrupt.
0: Disable LIN interrupts.
1: Enable LIN interrupt requests.
ECPR: Enable Comparator 0 Rising Edge Interrupt
This bit sets the masking of the CP0 Rising Edge interrupt.
0: Disable CP0 Rising Edge Interrupt.
1: Enable CP0 Rising Edge Interrupt.
ECPF: Enable Comparator 0 Falling Edge Interrupt
This bit sets the masking of the CP0 Falling Edge interrupt.
0: Disable CP0 Falling Edge Interrupt.
1: Enable CP0 Falling Edge Interrupt.
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EADC0: Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
EWADC0: Enable ADC0 Window Comparison Interrupt.
This bit sets the masking of the ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by the AD0WINT flag.
EREG0
R/W
Bit6
ELIN
R/W
Bit5
ECPR
R/W
Bit4
Rev. 1.3
ECPF
R/W
Bit3
EPCA0
R/W
Bit2
EADC0
R/W
Bit1
SFR Address:
EWADC0 00000000
R/W
Bit0
Reset Value
0xE6