C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 107
C8051F530-TB
Manufacturer Part Number
C8051F530-TB
Description
BOARD PROTOTYPE W/C8051F530
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F530-TB.pdf
(218 pages)
Specifications of C8051F530-TB
Contents
Board
Processor To Be Evaluated
C8051F52xA and C8051F53xA
Interface Type
USB
Lead Free Status / RoHS Status
Vendor undefined / Vendor undefined
For Use With/related Products
C8051F530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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11.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
ramp time increases (V
the power-on and V
delay (T
Note: The maximum V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset. The V
a power-on reset.
11.2. Power-Fail Reset / V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 11.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
monitor is enabled and is selected as a reset source after power-on resets; however its defined state
(enabled/disabled) is not altered by any other reset source. For example, if the V
RST
. An additional delay occurs before the device is released from reset; the delay decreases as the V
before V
PORDelay
Logic H IG H
Logic LO W
1.0
DD
V
RS T
) is typically less than 0.3 ms.
reaches the V
RST
DD
, the CIP-51 will be released from the reset state. Note that even though internal data
DD
/ RST
Figure 11.2. Power-On and V
DD
monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
ramp time is 1 ms; slower ramp times may cause the device to be released from reset
ramp time is defined as how fast V
RST
DD
level.
P ow er-O n
Monitor
R eset
C8051F52x/F52xA/F53x/F53xA
T
P O R D elay
Rev. 1.3
DD
Monitor Reset Timing
DD
DD
ramps from 0 V to V
to drop below V
M onitor
R eset
V D D
DD
monitor is enabled following
DD
RST
RST
monitor is disabled by
, the power supply
). Figure 11.2 plots
DD
DD
dropped below
VDD
settles above
DD
t
returns
107
DD
DD
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