C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 80
C8051F530-TB
Manufacturer Part Number
C8051F530-TB
Description
BOARD PROTOTYPE W/C8051F530
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F530-TB.pdf
(218 pages)
Specifications of C8051F530-TB
Contents
Board
Processor To Be Evaluated
C8051F52xA and C8051F53xA
Interface Type
USB
Lead Free Status / RoHS Status
Vendor undefined / Vendor undefined
For Use With/related Products
C8051F530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F52x/F52xA/F53x/F53xA
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
80
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–2: UNUSED. Read = 00b. Write = don’t care.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select
Reserved
R/W
Bit7
RESERVED. Read = 0b. Must write 0b.
UNUSED. Read = 0b. Write = don’t care.
CP0RIE: Comparator Rising-Edge Interrupt Enable.
0: Comparator rising-edge interrupt disabled.
1: Comparator rising-edge interrupt enabled.
CP0FIE: Comparator Falling-Edge Interrupt Enable.
0: Comparator falling-edge interrupt disabled.
1: Comparator falling-edge interrupt enabled.
Note: It is necessary to enable both CP0xIE and the correspondent ECPx bit located in EIE1
SFR.
These bits select the response time for Comparator0.
Note: Rising Edge response times are approximately double the Falling Edge response
times.
Mode
R/W
0
1
2
3
Bit6
—
CP0MD1
CP0RIE
R/W
Bit5
0
0
1
1
CP0MD0
CP0FIE
R/W
Bit4
0
1
0
1
Rev. 1.3
CP0 Falling Edge Response
Lowest Power Consumption
R/W
Bit3
—
Fastest Response Time
Time (TYP)
R/W
Bit2
—
—
—
CP0MD1 CP0MD0 00000010
R/W
Bit1
R/W
Bit0
SFR Address:
Reset Value
0x9D
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