C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 180
C8051F530-TB
Manufacturer Part Number
C8051F530-TB
Description
BOARD PROTOTYPE W/C8051F530
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F530-TB.pdf
(218 pages)
Specifications of C8051F530-TB
Contents
Board
Processor To Be Evaluated
C8051F52xA and C8051F53xA
Interface Type
USB
Lead Free Status / RoHS Status
Vendor undefined / Vendor undefined
For Use With/related Products
C8051F530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F52x/F52xA/F53x/F53xA
SFR Definition 17.17. LIN0MUL: LIN0 Multiplier Register
SFR Definition 17.18. LIN0ID: LIN0 ID Register
180
Bit7–6:
Bit5–1:
Bit0:
Bit7–6:
Bit5–0:
R/W
R/W
Bit7
Bit7
PRESCL[1:0]
PRESCL1–0: LIN Baud Rate Prescaler Bits.
These bits are the baud rate prescaler bits.
LINMUL4–0: LIN Baud Rate Multiplier Bits.
These bits are the baud rate multiplier bits. These bits are not used in slave mode.
DIV9: LIN Baud Rate Divider Most Significant Bit.
The most significant bit of the baud rate divider. The 8 least significant bits are in LIN0DIV.
The valid range for the divider is 200 to 511.
UNUSED. Read = 00b. Write = don’t care.
ID5–0: LIN Identifier Bits.
These bits form the data identifier.
If the LINSIZE bits (LIN0SIZE[3:0]) are 1111b, bits ID[5:4] are used to determine the data
size and are interpreted as follows:
00: 2 bytes
01: 2 bytes
10: 4 bytes
11: 8 bytes
R/W
R/W
Bit6
Bit6
R/W
R/W
Bit5
Bit5
R/W
R/W
Bit4
Bit4
LINMUL[4:0]
Rev. 1.3
R/W
R/W
Bit3
Bit3
ID[5:0]
R/W
R/W
Bit2
Bit2
R/W
R/W
Bit1
Bit1
DIV9
R/W
R/W
Bit0
Bit0
Address: 0x0D (indirect)
Address: 0x0E (indirect)
Reset Value
Reset Value
00000000
00000000
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