C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 111

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SFR Definition 11.2. RSTSRC: Reset Source
Note: Software should avoid read modify write instructions when writing values to RSTSRC.
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
—
UNUSED. Read = 1, Write = don't care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0.
1: Read: Source of last reset was Comparator0.
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit.
1: Read: Source of last reset was a write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout.
1: Read: Source of last reset was a Missing Clock Detector timeout.
detected.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the V
monitor as a reset source. Note: writing 1 to this bit before the V
and stabilized may cause a system reset. See register VDDMON (SFR Definition 11.1)
0: Read: Last reset was not a power-on or V
1: Read: Last reset was a power-on or V
nate.
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
FERROR C0RSEF
Write: Comparator0 is not a reset source.
Write: Comparator0 is a reset source (active-low).
Write: No Effect.
Write: Forces a system reset.
Write: Missing Clock Detector disabled.
Write: Missing Clock Detector enabled; triggers a reset if a missing clock condition is
Write: V
Write: V
Bit6
R
DD
DD
monitor is not a reset source.
monitor is a reset source.
R/W
Bit5
SWRSF
R/W
C8051F52x/F52xA/F53x/F53xA
Bit4
WDTRSF MCDRSF
Rev. 1.3
Bit3
R
DD
monitor reset; all other reset flags indetermi-
DD
monitor reset.
R/W
Bit2
PORSF
R/W
Bit1
DD
SFR Address:
monitor is enabled
PINRSF
Bit0
R
Reset Value
Variable
0xEF
DD
111