C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 133
C8051F530-TB
Manufacturer Part Number
C8051F530-TB
Description
BOARD PROTOTYPE W/C8051F530
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F530-TB.pdf
(218 pages)
Specifications of C8051F530-TB
Contents
Board
Processor To Be Evaluated
C8051F52xA and C8051F53xA
Interface Type
USB
Lead Free Status / RoHS Status
Vendor undefined / Vendor undefined
For Use With/related Products
C8051F530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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SFR Definition 13.13. P0SKIP: Port0 Skip
SFR Definition 13.14. P1MAT: Port1 Match
SFR Definition 13.15. P1MASK: Port1 Mask
Bits7–0: P1MAT[7:0]: Port1 Match Value.
Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits.
Bits7–0: P1MASK[7:0]: Port1 Mask Value.
R/W
R/W
Bit7
R/W
Bit7
Bit7
These bits control the value that unmasked P0 Port pins are compared against. A Port
Match event is generated if (P1 & P1MASK) does not equal (P1MAT & P1MASK).
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (V
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
These bits select which Port pins will be compared to the value stored in P1MAT.
0: Corresponding P1.n pin is ignored and cannot cause a Port Match event.
1: Corresponding P1.n pin is compared to the corresponding bit in P1MAT.
R/W
R/W
Bit6
R/W
Bit6
Bit6
R/W
R/W
Bit5
R/W
Bit5
Bit5
R/W
Bit4
R/W
R/W
Bit4
Bit4
C8051F52x/F52xA/F53x/F53xA
Rev. 1.3
R/W
R/W
Bit3
R/W
Bit3
Bit3
R/W
R/W
Bit2
R/W
Bit2
Bit2
R/W
R/W
Bit1
R/W
Bit1
Bit1
REF
SFR Address:
SFR Address:
SFR Address:
input, external oscil-
R/W
Bit0
R/W
R/W
Bit0
Bit0
Reset Value
00000000
Reset Value
00000000
11111111
Reset Value
0xCF
0xBF
0xD4
133
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