C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 173

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.7.2. LIN Indirect Access SFR Registers Definition
Table 17.4. LIN Registers* (Indirectly Addressable)
*These registers are used in both master and slave mode. The register bits marked with (m) are accessible
only in Master mode while the register bits marked with (s) are accessible only in slave mode. All other reg-
isters are accessible in both modes.
SFR Definition 17.4. LIN0DT1: LIN0 Data Byte 1
LIN0CTRL
LIN0SIZE
LIN0ERR
LIN0MUL
LIN0DT1
LIN0DT2
LIN0DT3
LIN0DT4
LIN0DT5
LIN0DT6
LIN0DT7
LIN0DT8
LIN0DIV
LIN0ST
Bit7–0:
LIN0ID
Name
R/W
Bit7
Address
LIN0DT1: LIN Data Byte 1.
Serial Data Byte 1 that is received or transmitted across the LIN interface.
0x0C
0x0D
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0E
R/W
Bit6
ENHCHK
STOP(s) SLEEP(s)
ACTIVE IDLTOUT ABORT(s) DTREQ(s) LININT ERROR WAKEUP
Bit7
PRESCL[1:0]
R/W
Bit5
Bit6
R/W
Bit4
C8051F52x/F52xA/F53x/F53xA
TXRX
Bit5
Rev. 1.3
R/W
Bit3
SYNCH(s) PRTY(s)
DTACK(s) RSTINT RSTERR WUPREQ STREQ(m)
Bit4
DIVLSB[7:0]
DATA1[7:0]
DATA2[7:0]
DATA3[7:0]
DATA4[7:0]
DATA5[7:0]
DATA6[7:0]
DATA7[7:0]
DATA8[7:0]
LINMUL[4:0]
R/W
Bit2
Bit3
ID[5:0]
R/W
Bit1
TOUT
Bit2
LINSIZE[3:0]
R/W
Bit0
Address:
CHK
Bit1
0x00 (indi-
00000000
Reset Value
BITERR
rect)
DONE
DIV9
Bit0
173