C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 122

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F52x/F52xA/F53x/F53xA
(F52x/F52xA) for the external CNVSTR signal, and any selected ADC or comparator inputs. The Crossbar
skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 13.3
shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP); Figure 13.4 shows the
Crossbar Decoder priority with the XTAL1 (P1.0) and XTAL2 (P1.1) pins skipped (P1SKIP = 0x03).
Important Note on UART Pins: On C8051F52xA/53xA devices, the UART pins must be skipped if the
UART is enabled in order for peripherals to appear on port pins beyond the UART on the crossbar. For
example, with the SPI and UART enabled on the crossbar with the SPI on P1.0-P1.3, the UART pins must
be skipped using P0SKIP for the SPI pins to appear correctly.
122
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped
Note: 4-Wire SPI Only.
TSSOP 20 and QFN 20
PIN I/O
TX0
RX0
TX0
RX0
SCK
MISO
MOSI
NSS*
LIN-TX
LIN-RX
CP0
CP0A
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
SF Signals
SF Signals
Port pin potentially assignable to peripheral
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
0
0
(TSSOP 20 and QFN 20)
1
0
P0SKIP[0:7] = 0x80
2
0
3
0
P0
Rev. 1.3
4
0
5
0
6
0
7
1
0
1
1
0
P1SKIP[0:7] = 0x01
C8051F53xA devices
C8051F53x devices
2
0
3
0
P1
4
0
5
0
6
0
7
0